Abstract: An integrated circuit is provided and includes first transistors of a first circuit arranged in a first cell row having a first number of fin structures and a second transistor of a second circuit. The second transistor is coupled in parallel with a first element in the first transistors between first and second terminals of the first circuit, and arranged in a second cell row having a second number, different from the first number, of fin structures. The first element and the second transistor share a first gate extending in a first direction to pass through the first and second cell rows in a layout view. The second transistor is a duplication of the first element.

Abstract: An electronic device including a foldable touch display panel and a driver circuit is provided. The foldable touch display panel includes a foldable substrate and a plurality of touch sensors. The foldable substrate includes a first portion and a second portion. The first portion and the second portion face each other in a folded state. The driver circuit is coupled to the foldable touch display panel. The driver circuit is configured to drive the foldable touch display panel to perform a touch sensing operation in a touch sensing state. The driver circuit is configured to determine a folding angle between the first portion and the second portion according to a capacitance variation of the touch sensors in the folded state.

Abstract: Methods, systems, and devices for contact foot wet pullback with liner wet punch are described. A first etching operation may be performed on a stack of materials and a first insulative material to form a plurality of segments including contacts, the contacts formed from a first conductive material of the stack of materials and extending at least partially through the first insulative material. A first liner material may be deposited over the segments and the first insulative material, and a directional gas bias operation may be performed to transform a portion of the first liner material in contact with an extension of the contacts into a second liner material. A second etching operation may be performed to remove the second liner material and expose a surface of the extension, and a third etching operation may be performed remove at least a portion of the extension.

Abstract: A light source is provided capable of maintaining the temperature of a collector surface at or below a predetermined temperature. The light source in accordance with various embodiments of the present disclosure includes a processor, a droplet generator for generating a droplet to create extreme ultraviolet light, a collector for reflecting the extreme ultraviolet light into an intermediate focus point, a light generator for generating pre-pulse light and main pulse light, and a thermal image capture device for capturing a thermal image from a reflective surface of the collector.

Abstract: A semiconductor device disclosed herein includes an interconnection structure over a substrate, a first magnetic layer over the interconnection structure, one or more conductive features over the first magnetic layer, a dielectric layer over the first magnetic layer and the one or more conductive features, and a second magnetic layer over the dielectric layer. In some embodiments, the one or more conductive features include a textured top surface.

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor, a first pull-up transistor and an output circuit. The input circuit is coupled to a first and second node, and is configured to receive a first and second enable signal, and to set a first control signal of the first node responsive to the first or second enable signal. The cross-coupled pair of transistors is coupled between the first and second node. The first pull-up transistor includes a first gate terminal configured to receive a clock input signal, a first drain terminal coupled to the second node, and a first source terminal coupled to a voltage supply. The output circuit is coupled between the second node and an output node, and configured to output an output clock signal responsive to the second control signal.

Abstract: A lithography system is provided capable of deterring contaminants, such as tin debris from entering into the scanner. The lithography system in accordance with various embodiments of the present disclosure includes a processor, an extreme ultraviolet light source, a scanner, and a hollow connection member. The light source includes a droplet generator for generating a droplet, a collector for reflecting extreme ultraviolet light into an intermediate focus point, and a light generator for generating pre-pulse light and main pulse light. The droplet generates the extreme ultraviolet light in response to the droplet being illuminated with the pre-pulse light and the main pulse light. The scanner includes a wafer stage. The hollow connection member includes an inlet that is in fluid communication with an exhaust pump. The hollow connection member provides a hollow space in which the intermediate focus point is disposed.

Abstract: Systems, methods, and devices are described herein for pre-setting scan flip-flops using combinational logic circuits. A system includes a plurality of flip-flop devices and a first pre-setting combinational logic circuit. The plurality of flip-flop devices are coupled together in series and configured to receive a scan input signal, capture data output from each flip-flop device of the plurality of flip-flop devices based on the scan input signal, and generate a scan output signal comprising the captured data. The first pre-setting combinational logic circuit is coupled to a first flip-flop device of the plurality of flip-flop devices. The first pre-setting combinational logic circuit includes a plurality of transistors and is configured to override and set either the scan input signal to the first flip-flop device or the scan output signal of the first flip-flop device based on selective operation of the plurality of transistors.

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a transmission circuit, and a slave latch including a first feedback inverter. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the transmission circuit includes a third transistor configured to receive the third clock signal.

Abstract: A cosmetic ester composition includes a trimellitic acid ester which is formed by subjecting a trimellitic acid and a C8-C13 alcohol to an esterification reaction, and a C5-C18 carboxylic acid polyol ester. The cosmetic ester composition has a hydroxyl value ranging from 5 mg KOH/g to 100 mg KOH/g, and a viscosity at 20° C. ranging from 150 cP to 1500 cP.

Abstract: A method for manufacturing an electronic device and a transferring head are provided. The method includes providing a plurality of microcomponents on a first substrate; providing a transferring head, wherein the transferring head includes a substrate and a head unit disposed on a side of the substrate, the head unit includes a layer, and the layer has a first portion and a second portion, wherein a thickness of the first portion is greater than a thickness of the second portion, and a difference between the thickness of the first portion and the thickness of the second portion is greater than or equal to 20 ?m and less than or equal to 70 ?m; contacting at least one microcomponent by a picking surface of the first portion; and transferring the microcomponent from the first substrate to a second substrate by the transferring head.

Abstract: Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.

Abstract: Managing a battery including measuring, in response to a first charging current and over a first time period, a first amperage and a first voltage of the cell at predetermined intervals; measuring, in response to a second charging current and over a second time period, a second amperage and a second voltage of the cell at the predetermined intervals; determining that the first amperage of the cell was maintained greater than a first threshold amount of time within the first time period, and in response, qualifying the first amperage and the first voltage as stable; determining that the second amperage of the cell was maintained greater than a second threshold amount of time within the second time period, and in response, qualifying the second amperage and the second voltage as stable; and in response to the qualifying, calculating a DCIR of the cell based on the voltages and the amperage.

Abstract: A semiconductor device includes several first cell row an several second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. A first row of the first cell rows is configured for a first cell to be arranged. The second cell rows extend in the first direction. Each of the second cell rows has a second row height that is different from the first row height. At least one row of the second cell rows includes a portion for at least one second cell to be arranged. The portion has a third row height that is different from the first row height and the second row height.

Abstract: Calibrating a battery including identifying a historical discharge rate of the battery; segmenting the historical discharge rate of the battery into regions; determining, based on the historical discharge rate of the battery, a first historical charge capacity of the battery for a first region and a second historical charge capacity of the battery for a second region; discharging, at an updated discharge rate, the battery from a first threshold voltage to a second threshold voltage; calculating, based on the updated discharge rate, a first updated charge capacity of the battery for the first region; determining a full charge capacity of the battery based on i) the first updated charge capacity of the battery for the first region and ii) the second historical charge capacity of the battery for the second region; adjusting a charging current of the battery based on the determined full charge capacity of the battery.

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

Abstract: A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor of a first type and a first pull-up transistor of the first type. The input circuit is configured to set a first control signal of a first node in response to a first or second enable signal. The cross-coupled pair of transistors is coupled between the first node and an output node. The first transistor is coupled between the first and a second node. The first pull-up transistor includes a first gate terminal, a first drain terminal and a first source terminal. The first gate terminal is configured to receive an inverted clock input signal. The first drain terminal is coupled to the second node and the first transistor. The first pull-up transistor is configured to adjust a clock output signal responsive to the inverted clock input signal.

Abstract: Computer systems, methods, and apparatuses for estimating changes in gas emissions are described. A computer system may monitor overall emission levels based on sensor outputs from a plurality of gas sensors in a facility. The computer system may estimate a total emission level over a time interval based on the accumulative, gas-response-factor weighted detections of the gas sensors. Emissions from maintenance activities may be excluded as appropriate. The total emission level may be compared with total emission level estimated from different time intervals and/or different facilities. The computer system may be further used for comparing emissions across multiple facilities, or emissions from facilities across multiple regions.

Abstract: An antenna structure includes a grounding element, a first, a second and a third radiation portion, a shorting radiation portion, a grounding radiation portion, a dielectric substrate, and a first conductive via element. The first radiation portion and the second radiation portion are coupled to a feeding point. The second radiation portion is coupled to the grounding element through the shorting radiation element. The third radiation portion is coupled to the grounding element. A first coupling gap is formed between the grounding radiation element and the grounding element. The dielectric substrate has a first surface and a second surface which are opposite to each other. The first radiation portion is disposed on the first surface. The third radiation portion is disposed on the second surface. The third radiation portion is coupled to the first radiation portion through the first conductive via element.

Abstract: A light source is provided capable of maintaining the temperature of a collector surface at or below a predetermined temperature. The light source in accordance with various embodiments of the present disclosure includes a processor, a droplet generator for generating a droplet to create extreme ultraviolet light, a collector for reflecting the extreme ultraviolet light into an intermediate focus point, a light generator for generating pre-pulse light and main pulse light, and a thermal image capture device for capturing a thermal image from a reflective surface of the collector.