Patents by Inventor Ying Lin

Ying Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009824
    Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Seid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Hui-Zhong Zhuang, Chi-Lin Liu
  • Patent number: 12009341
    Abstract: An integrated antenna package structure includes a first redistribution structure, a first chip, a heat dissipation structure, a second chip, and an antenna structure. The first chip is located on a first side of the first redistribution structure, and is electrically connected to the first redistribution structure. The heat dissipation structure is thermally connected to the first chip, and the first chip is located between the heat dissipation structure and the first redistribution structure. The second chip is located on a second side of the first redistribution structure opposite to the first side, and is electrically connected to the first redistribution structure. The antenna structure is electrically connected to the first redistribution structure.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: June 11, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Po-Kai Chiu, Sheng-Tsai Wu, Yu-Min Lin, Wen-Hung Liu, Ang-Ying Lin, Chang-Sheng Chen
  • Patent number: 11994503
    Abstract: Computer systems, methods, and apparatuses for estimating changes in gas emissions are described. A computer system may monitor overall emission levels based on sensor outputs from a plurality of gas sensors in a facility. The computer system may estimate a total emission level over a time interval based on the accumulative, gas-response-factor weighted detections of the gas sensors. Emissions from maintenance activities may be excluded as appropriate. The total emission level may be compared with total emission level estimated from different time intervals and/or different facilities. The computer system may be further used for comparing emissions across multiple facilities, or emissions from facilities across multiple regions.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: May 28, 2024
    Assignee: Molex, LLC
    Inventors: Wenfeng Peng, Ling-Ying Lin, Alissa Nedossekina
  • Patent number: 11985238
    Abstract: Embodiments disclose a vehicle-mounted device upgrade method and a related device. The method may be applied to an intelligent vehicle, the intelligent vehicle includes a vehicle-mounted control device, and the method may include: receiving, by the vehicle-mounted control device, a first partial key sent by the communications device; restoring, by the vehicle-mounted control device, a first key by using the first partial key and a second partial key that is stored on the vehicle-mounted control device; and performing, by the vehicle-mounted control device, secure processing on a first upgrade file by using the first key, to obtain the securely processed first upgrade file, where the secure processing includes generating first message authentication code (MAC), and the securely processed first upgrade file includes the first upgrade file and the first MAC. According to this application, the vehicle-mounted device can be securely and efficiently upgraded.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 14, 2024
    Assignee: Huawei International Pte. Ltd.
    Inventors: Yanjiang Yang, Zhuo Wei, Hsiao-Ying Lin, He Wei, Junqiang Shen
  • Publication number: 20240154309
    Abstract: A multi-band antenna includes a substrate with a first surface and a second surface, a first antenna structure with a first antenna coupling segment, a second antenna structure with a second antenna coupling segment, a first grounding section, a coupling section, a via hole, and a second grounding section. Both of the first antenna structure and the second antenna structure are disposed on the first surface. The first grounding section is connected to the first antenna coupling segment. The coupling section is disposed on the second surface and projected onto the first surface to form a coupling region. Both of the first antenna coupling segment and the second antenna coupling segment at least partially overlap the coupling region. The via hole penetrates through the substrate and is connected between the coupling section and the second antenna coupling segment. The second grounding section is connected to the coupling section.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 9, 2024
    Inventors: Hung-Ying LIN, Wen Tai TSENG, Kuo Jen LAI
  • Publication number: 20240153924
    Abstract: A manufacturing method of an electronic device is disclosed by the present disclosure. The manufacturing method includes providing a substrate, wherein the substrate includes a plurality of working areas, and each of the plurality of working areas includes a plurality of first recesses and a plurality of second recesses; disposing a plurality of first electronic units in the plurality of first recesses of the plurality of working areas through fluid transfer; identifying a defective working area from the plurality of working areas, wherein at least one of the plurality of first recesses of the defective working area has no electronic unit or a defective first electronic unit disposed therein; and disposing at least one repairing electronic unit in at least one of the plurality of second recesses of the defective working area through laser transfer.
    Type: Application
    Filed: October 3, 2023
    Publication date: May 9, 2024
    Applicant: InnoLux Corporation
    Inventors: Fang-Ying Lin, Kai Cheng, Ming-Chang Lin, Tsau-Hua Hsieh
  • Publication number: 20240147689
    Abstract: Integrated circuits (ICs) and methods are provided. An IC includes a charge-storing device. The charge-storing device includes a first charge-storing stack extending into a substrate, and a second charge-storing stack extending into the substrate and adjacent to the first charge-storing stack along a first direction. The first charge-storing stack and the second charge-storing stack extend lengthwise along a second direction perpendicular to the first direction, and the first charge-storing stack and the second charge-storing stack have an offset along the second direction, the offset being greater than zero.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Hsun Lin, Jyun-Ying Lin
  • Patent number: 11973067
    Abstract: Methods for manufacturing a display device are provided. The methods include providing a plurality of light-emitting units and a substrate. The methods also include transferring the light-emitting units to a transfer head. The methods further include attaching at least one of the plurality of light-emitting units on the transfer head to the substrate by a bonding process, wherein the transfer head and the substrate satisfy the following equation during the bonding process: 0 ? ? ? T ? ? 1 T ? ? 2 ? A ? ( T ) ? dT - ? T ? ? 1 T ? ? 3 ? E ? ( T ) ? dT ? ? < 0.01 wherein A(T) is the coefficient of thermal expansion of the transfer head, E(T) is the coefficient of thermal expansion of the substrate, T1 is room temperature, T2 is the temperature of the transfer head, and T3 is the temperature of the substrate.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 30, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Fang-Ying Lin, Kai Cheng, Hui-Chieh Wang, Shun-Yuan Hu
  • Publication number: 20240135846
    Abstract: An electronic device and a manufacturing method thereof are provided. The manufacturing method of the electronic device includes the following. A substrate is provided. A plurality of electronic units are transferred to the substrate. The electronic units are inspected to obtain M first defect maps. The M first defect maps are integrated into N second defect maps, where N<M. M repairing groups are provided according to the N second defect maps. Each of the repairing groups includes at least one repairing electronic unit. The M repairing groups are transferred to the substrate. At least two of the repairing groups have the same location distribution of repairing electronic units, and the location distribution is consistent with a defect distribution of one of the second defect maps.
    Type: Application
    Filed: September 17, 2023
    Publication date: April 25, 2024
    Applicant: Innolux Corporation
    Inventors: Kai Cheng, Fang-Ying Lin, Ming-Chang Lin, Tsau-Hua Hsieh
  • Publication number: 20240131808
    Abstract: A tape laying device includes a tape transmission mechanism, a compaction head mechanism, a cutter mechanism, a heating mechanism and a motion mechanism. The tape transmission mechanism is configured to transmit the pre-impregnated tape. The compaction head mechanism, connected with the tape transmission mechanism, is configured to depress and drive the pre-impregnated tape transmitted by the tape transmission mechanism to follow a moving path so as to adhere the pre-impregnated tape onto the mould surface. The cutter mechanism is configured to cut the pre-impregnated tape. The heating mechanism, disposed downstream to the cutter mechanism, is configured to heat the pre-impregnated tape. The motion mechanism is used to have the cutter mechanism having an active path to move toward the moving path while the cutter mechanism cuts the pre-impregnated tape.
    Type: Application
    Filed: December 7, 2022
    Publication date: April 25, 2024
    Inventors: TENG-YEN WANG, SHUN-SHENG KO, MIAO-CHANG WU, TUNG-YING LIN, CHAO-HONG HSU
  • Publication number: 20240122163
    Abstract: The present invention demonstrated a Cre-loxP based cofilin-1 transgenic animal model to address the pathophysiological role of over-expressed cofilin-1 on systemic development.
    Type: Application
    Filed: February 6, 2023
    Publication date: April 18, 2024
    Inventors: Yi-Jang LEE, Yu-Chuan LIN, Min-Ying LIN, Bing-Ze LIN, Chia-Yun KANG
  • Patent number: 11955579
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of light-emitting elements on a first substrate and forming a first pattern array on a second substrate, wherein the first pattern array includes an adhesive layer. The method also includes transferring the plurality of light-emitting elements from the first substrate to the second substrate and forming the first pattern array on a third substrate. The method includes transferring the plurality of light-emitting elements from the second substrate to the third substrate, and reducing an adhesion force of a portion of the adhesive layer. The method also includes forming a second pattern array on a fourth substrate, and transferring the plurality of light-emitting elements from the third substrate to the fourth substrate. The pitch between the plurality of light-emitting elements on the first substrate is different than the pitch of the first pattern array.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 9, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
  • Patent number: 11949040
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of diodes on a first substrate and forming a first pattern array on a second substrate. The method also includes transferring the plurality of diodes from the first substrate to the second substrate. The method further includes forming the first pattern array on a third substrate. In addition, the method includes transferring the plurality of diodes from the second substrate to the third substrate. The method also includes forming a second pattern array on a fourth substrate. The method further includes transferring the plurality of diodes from the third substrate to the fourth substrate. The pitch between the plurality of diodes on the first substrate is different from the pitch of the first pattern array.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 2, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Kai Cheng, Tsau-Hua Hsieh, Fang-Ying Lin, Tung-Kai Liu, Hui-Chieh Wang, Chun-Hsien Lin, Jui-Feng Ko
  • Patent number: 11943914
    Abstract: A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: March 26, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Yu-Ying Lin
  • Patent number: 11943939
    Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Kai Hsu, Jerry Chang Jui Kao, Chin-Shen Lin, Ming-Tao Yu, Tzu-Ying Lin, Chung-Hsing Wang
  • Publication number: 20240096857
    Abstract: An electronic device includes a substrate, a spacer, a first element and a second element. The spacer is disposed on the substrate and has a first portion, a second portion, a first opening, a second opening and a third opening arranged in a first direction. In a cross-section view, the second opening is located between the first opening and the third opening, the first portion is located between the first opening and the second opening, and the second portion is located between the second opening and the third opening. A width of the first portion is less than a width of the second portion in the first direction, and an area of the second opening is different from an area of the first opening. The first element is overlapped with the first opening. The second element is overlapped with the third opening.
    Type: Application
    Filed: December 4, 2023
    Publication date: March 21, 2024
    Applicant: Innolux Corporation
    Inventors: Jian-Jung Shih, Tsau-Hua Hsieh, Fang-Ying Lin, Kai Cheng
  • Publication number: 20240097520
    Abstract: An axial flux motor includes a rotor assembly and a stator assembly. The rotor assembly has magnets. The stator assembly has a circuit substrate, segmented iron cores, and a coil. The circuit substrate extends radially. The segmented iron cores are supported on the circuit substrate to be opposite to the magnet in the axial direction. Segmented iron cores arranged in the circumferential direction. A coil is sleeved on a segmented iron core. Holding seats of an insulating material correspond respectively to the segmented iron cores. A holding seat abuts with and covers a segmented iron core from both axial sides and the circumferential direction, and is used for winding the coil. The circuit substrate has slot holes. A slot hole is used for embedding and positioning a portion of a holding seat that protrudes more towards one axial side than the coil.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 21, 2024
    Inventors: Keng-Chang WU, Guo-Jhih YAN, Hsiu-Ying LIN, Kuo-Min WANG
  • Publication number: 20240097661
    Abstract: A scan flip-flop circuit includes a selection circuit including first and second input terminals coupled to first and second I/O nodes, a flip-flop circuit coupled to the selection circuit, a first driver coupled between the flip-flop circuit and the first I/O node, and a second driver coupled between the flip-flop circuit and the second I/O node. The selection circuit and drivers receive a scan direction signal. In response to a first logic level of the scan direction signal, the selection circuit responds to a first signal received at the first input terminal, and the second driver outputs a second signal responsive to a flip-flop circuit output signal. In response to a second logic level of the scan direction signal, the selection circuit responds to a third signal received at the second input terminal, and the first driver outputs a fourth signal responsive to the flip-flop circuit output signal.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 21, 2024
    Inventors: Huaixin XIAN, Tzu-Ying LIN, Liu HAN, Jerry Chang Jui KAO, Qingchao MENG, Xiangdong CHEN
  • Patent number: D1024932
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: April 30, 2024
    Assignee: WALSIN LIHWA CORPORATION
    Inventors: Ko-Ming Chen, Shih-Hsiang Wang, An-Hung Lin, Min-Chuan Wu, Shao-Pei Lin, Chien-Chung Ni, Chun-Ying Lin
  • Patent number: D1025886
    Type: Grant
    Filed: December 21, 2023
    Date of Patent: May 7, 2024
    Assignee: Xiamen Jingwei Supply Chain Management Co., Ltd
    Inventor: Ying Lin