Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

Abstract: A resistive random-access memory structure and a method for fabricating a resistive random-access memory structure are described. A first dielectric layer is formed on a substrate. A plurality of bottom electrodes are independently embedded in the first dielectric layer. A transition metal oxide layer covers the plurality of bottom electrodes and extends onto a portion of the first dielectric layer. The minimum distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance. The first distance is in a range of 10 nm to 200 ?m. A top electrode is formed on the transition metal oxide layer.

Abstract: An antenna coupling device is disclosed. The device includes a first isolator that includes an input port and an output port and a first circulator that includes a first port, a second port, and a third port. The first port of the first circulator is coupled with the output port of the first isolator; and the second port of the first circulator is configured for coupling with a first antenna. The device also includes a second isolator that includes an input port and an output port. The input port of the second isolator is coupled with the third port of the first circulator.

Abstract: An exemplary system comprises a linearizer module, a first upconverter module, a power amplifier module, a signal sampler module, and a downconverter module. The linearizer module may be configured to receive a first intermediate frequency signal and to adjust the first intermediate frequency signal based on a reference signal and a signal based on a second intermediate frequency signal. The first upconverter module may be configured to receive and up-convert a signal based on the adjusted first intermediate frequency signal to a radio frequency signal. The power amplifier module may be configured to receive and amplify a power of a signal based on the radio frequency signal. The signal sampler module may be configured to sample a signal based on the amplified radio frequency signal. The downconverter module may be configured to receive and down-convert a signal based on the sampled radio frequency signal to the second intermediate frequency signal.

Abstract: Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assist in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assist in impedance matching.

Abstract: Expression-enhancing nucleotide sequences for eukaryotic expressions systems are provided that allow for enhanced and stable expression of recombinant proteins in eukaryotic cells. Genomic integration sites providing enhanced expression and methods of use thereof are provided for expression of a gene of interest in a eukaryotic cell. Chromosomal loci, sequences, and vectors are provided for enhanced and stable expression of genes in eukaryotic cells.

Abstract: A selection of a plurality of graphical user interface (GUI) components of a GUI is received. The selection is received so that the GUI can be tested. Attributes of the selection of GUI components are determined. Using the attributes, a default procedure for testing the GUI is determined. The default procedure includes a first set of input values for GUI components of the plurality of GUI components. The default procedure includes a first sequence in which the first set of input values are provided. Modifications to the default procedure are received. Using the modifications, a final procedure with a second set of input values provided in a sequence is generated. The GUI is tested with the final procedure. Testing the GUI includes providing the second set of input values to respective GUI components in the second sequence.

Abstract: A digital microwave radio system includes a splitter that splits a common baseband input into two baseband outputs, first and second transmitters, each transmitter electrically connected to a baseband output of the splitter via a mixer, a common local oscillator electrically connected to the mixer of the first transmitter and the mixer of the second transmitter via an adjustable phase shifter, respectively, and a combiner. The common local oscillator is configured to up-convert each baseband output into a radio-frequency signal using a corresponding mixer. The combiner combines the two radio-frequency signals into a 0-degree phase-shift output and a 180-degree phase-shift output, respectively. A phase error control loop adjusts the phase shifter to minimize the 180-degree phase-shift radio-frequency output. A combiner gain control loop adjusts the output power level of the two transmitters in accordance with an actual power detector reading at the 0-degree phase-shift radio-frequency output.

Abstract: Systems and methods for improved chip device performance are discussed herein. An exemplary chip device for use in an integrated circuit comprises a bottom and a top opposite the bottom. The chip device comprises a through-chip device interconnect and a clearance region. The through-chip device interconnect is configured to provide an electrical connection between a ground plane trace on the bottom and a chip device path on the top of the chip device. The clearance region on the bottom of the chip device comprises an electrically conductive substance. The size and shape of the clearance region assists in impedance matching. The chip device path on the top of the chip device may further comprise at least one tuning stub. The size and shape of the at least one tuning stub also assists in impedance matching.

Abstract: Expression-enhancing nucleotide sequences for eukaryotic expressions systems are provided that allow for enhanced and stable expression of recombinant proteins in eukaryotic cells. Genomic integration sites providing enhanced expression and methods of use thereof are provided for expression of a gene of interest in a eukaryotic cell. Chromosomal loci, sequences, and vectors are provided for enhanced and stable expression of genes in eukaryotic cells.

Abstract: The invention provides a non-volatile memory device and methods for fabricating the same. The non-volatile memory device includes a non-volatile memory cell including a first transistor and a second transistor disposed on a substrate. The first and second transistors commonly use a first source region. A first gate of the first transistor and a second gate of the second transistor are different portions of a word line. First and second resistive switching elements are coupled to a first drain region of the first transistor and a second drain region of the second transistor. A first source line is coupled to the source region. First and second bit lines are coupled to the first and second resistive switching elements. The first source line, the first and second bit lines belong to a metal layer and are parallel to each other.

Abstract: An antenna RSSI meter includes a microcontroller unit for digitizing an antenna receiver voltage signal, converting the digitized antenna receiver voltage signal into a receiver signal level in accordance with a predefined antenna specification, and converting the receiver signal level into the antenna tuning signal in accordance with the predefined antenna specification. The antenna RSSI meter includes an input communication port for receiving the antenna receiver voltage signal from an antenna and providing the antenna receiver voltage signal to the microcontroller unit, The antenna RSSI meter also includes an output communication port for receiving the antenna tuning signal from the microcontroller unit and providing the antenna tuning signal to an antenna auto-aligning mechanism for adjusting position and orientation of the antenna.

Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

Abstract: A selection of a plurality of graphical user interface (GUI) components of a GUI is received. The selection is received so that the GUI can be tested. Attributes of the selection of GUI components are determined. Using the attributes, a default procedure for testing the GUI is determined. The default procedure includes a first set of input values for GUI components of the plurality of GUI components. The default procedure includes a first sequence in which the first set of input values are provided. Modifications to the default procedure are received. Using the modifications, a final procedure with a second set of input values provided in a sequence is generated. The GUI is tested with the final procedure. Testing the GUI includes providing the second set of input values to respective GUI components in the second sequence.

Abstract: A selection of a plurality of graphical user interface (GUI) components of a GUI is received. The selection is received so that the GUI can be tested. Attributes of the selection of GUI components are determined. Using the attributes, a default procedure for testing the GUI is determined. The default procedure includes a first set of input values for GUI components of the plurality of GUI components. The default procedure includes a first sequence in which the first set of input values are provided. Modifications to the default procedure are received. Using the modifications, a final procedure with a second set of input values provided in a sequence is generated. The GUI is tested with the final procedure. Testing the GUI includes providing the second set of input values to respective GUI components in the second sequence.

Abstract: A radio-frequency (RF) component includes a first portion of a waveguide configured to transmit an electro-magnetic (EM) wave. The RF component includes a waveguide coupling configured to receive the EM wave from the first portion of the waveguide and transmit the EM wave to an external RF component. The waveguide coupling includes a waveguide plate having a second portion of the first waveguide formed therein; a waveguide spacer having a third portion of the first waveguide formed therein; and a conductive spring circumferentially disposed around the first waveguide in between the waveguide plate and the waveguide spacer.

Abstract: A resistive random-access memory structure and a method for fabricating a resistive random-access memory structure are described. A first dielectric layer is formed on a substrate. A plurality of bottom electrodes are independently embedded in the first dielectric layer. A transition metal oxide layer covers the plurality of bottom electrodes and extends onto a portion of the first dielectric layer. The minimum distance between the bottom electrode and a sidewall of the transition metal oxide layer is a first distance. The first distance is in a range of 10 nm to 200 ?m. A top electrode is formed on the transition metal oxide layer.

Abstract: Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

Abstract: Disclosed is a hair treatment composition comprising from 0.00001 to 1% zinc salt by weight of the composition, from 0.2 to 2% non-ionic surfactant by weight of the composition, and a preservative system comprising an antimicrobial urea derivative.