Abstract: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.

Abstract: A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the substrate. The sinker has the second type conductivity, and is located in the epitaxial layer. The sinker extends from the substrate to an upper surface of the epitaxial layer, and partitions a region off from the epitaxial layer. The active device is located within the region. The first buried layer has the first type conductivity, and is located between the region and the substrate. The second buried layer has the second type conductivity, and is located between the first buried layer and the substrate. The second buried layer connects with the sinker. Because of the above-mentioned configuration, latch-up can be prevented.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first epitaxial layer, a first sinker, a first buried layer, a second epitaxial layer, a second sinker and a second buried layer. The first and second epitaxial layers are disposed sequentially on the substrate. The first sinker and the first buried layer define a first area from the first and the second epitaxial layers. The second sinker and the second buried layer define a second area from the second epitaxial layer in the first area. An active device is disposed in the second area. The first buried layer is disposed between the first area and the substrate, and is connected to the first sinker. The second buried layer is disposed between the second area and the first epitaxial layer, and is connected to the second sinker.

Abstract: A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second sinker, a first buried layer and a second buried layer. The first and the second epitaxial layer are sequentially disposed on the substrate. The first sinker and the first buried layer separate a first region from the second epitaxial layer. The second sinker and the second buried layer separate a second region from the second epitaxial layer. The well is disposed in the first region. A first transistor is disposed in the well. A second transistor is disposed in the second region. A deep trench isolation is disposed between the first and the second region and extends from the substrate to the upper surface of the second epitaxial layer.

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract: Systems and methods for asynchronous multi-channel data communications are provided. In one embodiment, a system in accordance with the invention includes a plurality of redundant pairs of computer systems, a plurality of actuators, and a plurality of line replaceable units. Each of the line replaceable units is coupled to one of the actuators, and each of the line replaceable units is configured to receive synchronous digital control data from each pair of computer systems of the plurality of redundant pairs of computer systems. The plurality of redundant pairs of computer systems includes at least three redundant pairs of computer systems, and the plurality of line replaceable units includes three or more line replaceable units.

Abstract: A system providing mid-value selection (MVS) for control command output in a fly-by-wire system where the fly-by-wire systems includes a plurality of primary flight computers (PFCs) receiving data through integrated flight control buses from actuation control electronics (ACE) for flight crew and status sensor inputs, the PFCs providing data through the flight control buses to the ACE for control signal output, provides elements for receiving in an ACE data from each PFC and receiving a data valid signal with respect to each PFC. Fresh data for each PFC is selected as the data received or past MVS output responsive to the respective data valid signal. Based on a predetermined criterion the system chooses from the PFC fresh data a selected set of PFC fresh data as the MVS output and stores the MVS output for use.

Abstract: A system for detecting the processing speed of an integrated circuit (IC) includes a flip-flop, a delay module, and a judge unit. The flip-flop receives a clock signal as a trigger signal and generates an inverted output signal. The delay module receives the inverted output signal, adjusts the delay time of the inverted output signal according to a selection signal, and outputs a delay signal to the flip-flop to have the flip-fop generate the output signal. The judge unit receives the output signal and generates a judge signal, which is enabled when the clock period of the output signal is longer than that of the clock signal.

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract: The present invention is related to a method for patching a firmware in a memory device. At least one functional patching program is stored at a read/write memory location inside the memory device, thereby correcting or updating a functional program in the firmware. Once the function is used, it can be directly replaced by the program stored in the memory location without re-burning or replacing the whole firmware so that the purposes of reducing cost and simplifying update firmware can be achieved.

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract: Systems and methods for asynchronous multi-channel data communications are provided. An embodiment of the invention includes a minimum of three channels for digital computation in Primary Flight Computers and four channels for digital/analog conversion in Actuation Control Electronics. Each channel (Primary Flight Computer or Actuation Control Electronics) contains two computation lanes with dissimilar processors and compilers. Hence with dual-dissimilar processors the computer architecture is fail-passive to generic errors. The two Actuation Control Electronics computation lanes select the digital control data of one of the two computation lanes of one of the three digital computation channels for conversion and transmission to associated actuators.

Abstract: A method to reduce the inverse narrow width effect in NMOS transistors is described. An oxide liner is deposited in a shallow trench that is formed to isolate active areas in a substrate. A photoresist plug is formed in the shallow trench and is recessed below the top of the substrate to expose the top portion of the oxide liner. An angled indium implant through the oxide liner into the substrate is then performed. The plug is removed and an insulator is deposited to fill the trenches. After planarization and wet etch steps, formation of a gate dielectric layer and a patterned gate layer, the NMOS transistor exhibits an improved Vt roll-off of 40 to 45 mVolts for both long and short channels. The improvement is achieved with no degradation in junction or isolation performance. The indium implant dose and angle may be varied to provide flexibility to the process.

Abstract: A method and an apparatus for booting a computer with a memory card are disclosed. The apparatus has a portable memory card and a memory card controller chipset for booting a computer. The embedded operating system in the memory card is provided for booting the computer in a prompt, convenient and simplified manner. In addition, a user is allowed to launch applications installed in the memory card after the computer is booted.

Abstract: A transparent cube with picture displaying function comprising a transparent body and a plurality of transparent boards surrounded the transparent body, characterized in that the four side walls of the transparent body are provided with at least two small holes containing small magnet therein, and the inner side wall of the four transparent boards are provided with at least two small holes corresponding to the small holes of the transparent body and also containing a small magnet therein; when the transparent body contacts with the four transparent boards face to face, the transparent body is firmly secured together with the four transparent boards as a result of attraction force between the small magnets, and a picture (or photograph) is inserted in between the contact face of the transparent body and the four transparent boards such that the transparent cube can provides four displayed pictures for appreciation.

Abstract: An electric automatic pop-up toaster has a carriage and a pivotably connected manually operative arm for moving the carriage to a lowermost position for toasting in well-known manner. At the beginning of each toasting cycle, the arm is horizontal and a latching plate is magnetically held down to hold the arm and the carriage in a lowermost position. The arm presses against a wire spring to hold closed a power switch (not shown) that supplies power to heating elements of the toaster. The latching plate is (magnetically) released at the end of each toasting cycle by a timer. This allows the carriage to move upwards to pop-up toasted bread in a usual way. However should the carriage fail to move upwards when the latching plate is released, the arm is pivoted by a spring and tilted to the position shown in the Figure. The wire is therefore released and enters a slot in a bracket mounted to the carriage. The switch opens and remains open to prevent power being re-instated to the heating elements.