Abstract: A method of producing a heterophase graphite, including the steps of (A) providing a silicon carbide single-crystal substrate;(B) placing the silicon carbide single-crystal substrate in a graphite crucible and then in a reactor to undergo an air extraction process; and (C) performing a desilicification reaction on the silicon carbide single-crystal substrate in an inert gas atmosphere to obtain 2H graphite and 3R graphite, so as to directly produce lumpy (sheetlike, crushed, particulate, and powderlike) 2H graphite and 3R graphite, and preclude secondary contamination of raw materials which might otherwise occur because of a crushing step, an oxidation step, and an acid rinsing step.

Abstract: The present disclosure describes combination therapies comprising an antagonist of Programmed Death 1 receptor (PD-1) and a Toll-like receptor 9 (TLR9) agonist that is a CpG-C type oligonucleotide, and the use of the combination therapies for the treatment of cancer.

Abstract: A low-density parity-check (LDPC) apparatus and a matrix trapping set breaking method are provided. The LDPC apparatus includes a logarithm likelihood ratio (LLR) mapping circuit, a variable node (VN) calculation circuit, an adjustment circuit, a check nodes (CN) calculation circuit and a controller. The LLR mapping circuit converts an original codeword into a LLR vector. The VN calculation circuit calculates original V2C information by using the LLR vector and C2V information. The adjustment circuit adjusts the original V2C information to get adjusted V2C information in accordance with a factor. The CN calculation circuit calculates the C2V information by using the adjusted V2C information, and provides the C2V information to the VN calculation circuit. The controller determines whether to adjust the factor. When LDPC iteration operation falls into matrix trap set, the controller decides to adjust the factor so that the iteration operation breaks away from the matrix trap set.

Abstract: The LDPC apparatus includes an LDPC iteration calculating circuit, a decision-bit storage circuit, and a convergence detection circuit. The LDPC iteration calculating circuit performs an LDPC iteration calculation to obtain a new decision bit value of a corresponding variable node. The decision-bit storage circuit uses the new decision bit value to update one corresponding old decision bit value among a plurality of old decision bit values. The convergence detection circuit stores check sums of a plurality of check nodes. The convergence detection circuit uses the new decision bit value and the corresponding old decision bit value to update one corresponding check sum among the check sums. The convergence detection circuit determines whether the LDPC iteration calculation is converged based on the check sums of the check nodes.

Abstract: A non-volatile memory (NVM) apparatus and a garbage collection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller is coupled to the NVM. The controller accesses the NVM according to a logical address of a write command of a host. The controller performs the garbage collection method to release space occupied by invalid data. The garbage collection method includes: grouping a plurality of blocks of the NVM into a plurality of tiers according to hotness of data, moving valid data in one closed source block of a hotter tier among the tiers to one open target block of a cooler tier among the tiers, and erasing the closed source block of the hotter tier to release space.

Abstract: The present disclosure describes combination therapies comprising an anti-IL-10 antibody or antigen-binding fragment thereof and a CpG-C type oligonucleotide, and the use of the combination therapies for the treatment of cancer.

Abstract: A non-volatile memory (NVM) apparatus and an iteration sorting method thereof are provided. The NVM apparatus performs the iteration sorting method to select one target block from a plurality of blocks of a NVM, and to perform a management operation on the target block. The iteration sorting method includes: selecting a plurality of candidate blocks among the blocks of the NVM to join into a sorting set, sorting all of the candidate blocks in the sorting set according to metadata, picking one candidate block with maximum (or minimum) metadata from the sorting set to serve as the target block, and keeping M candidate blocks in the sorting set and discarding the rest of the candidate blocks from the sorting set.

Abstract: The present disclosure relates to a system which includes a memory controller interface, a memory unit interface, and a correction block. The memory controller interface includes a digitally-controlled delay line (DCDL). The memory unit interface is coupled to the memory controller interface, and is configured to communicate with the memory controller interface through a first signal and a second signal. The correction block is configured to determine a result of alignment between the first signal and the second signal, and to provide a correction signal configured to align the first signal to the second signal. Other systems, devices and methods are disclosed.

Abstract: A non-volatile memory (NVM) apparatus and an address classification method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller accesses the NVM in accordance with a write command of a host. The controller may perform the address classification method. The address classification method includes: providing a data look-up table, wherein the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value; searching the data look-up table based on the logical address of the write command in order to obtain a corresponding counter value and a corresponding timer value; and determining whether the logical address of the write command is a hot data address based on the corresponding counter value and the corresponding timer value.

Abstract: The invention provides a delivery system comprising a cell penetrating peptide, 10 histidines, and an interfering RNA molecule. The system can be used for delivering interfering RNA molecules into a cell in vivo or in vitro. Therapeutic uses for the delivery system are also provided.

Abstract: A method of producing a carbide raw material includes the steps of (A) providing a porous carbon material and a high-purity silicon raw material or a metal raw material and applying the porous carbon material and the high-purity silicon raw material or a metal raw material alternately to form a layer structure; (B) putting the layer structure in a synthesis furnace to undergo a gas evacuation process; and (C) producing a carbide raw material with a synthesis reaction which the layer structure undergoes in an inert gas atmosphere, wherein the carbide raw material is a carbide powder of a particle diameter of less than 300 ?m, thereby preventing secondary raw material contamination otherwise arising from comminution, oxidation and acid rinsing.

Abstract: A color mark structure applying on rubber product comprises cellophane and a transfer paper. The transfer paper is arranged on the cellophane and a predetermined color or a predetermined pattern with a predetermined color is printed thereon by screen printing. The transfer paper having the predetermined color or the predetermined pattern with the predetermined color and the cellophane are attached on the rubber product. The upper and lower sides of the transfer paper are respectively connected with the cellophane and the rubber product.

Abstract: A method, computer program product, and system for generating and embedding a watermark in digital video frame include a processor obtaining a request to generate a watermark and embed the watermark in a digital video frame captured by a first monitor. Based on obtaining the request, the processor fetches from one or more pre-defined regions of a memory resource, digital video data captured by at least two monitors, where a timestamp of the digital video data is equal to a timestamp of the digital video frame. The processor generates a watermark from the digital video data by calculating a binary result of the digital video data. The processor embeds the watermark (binary result) in the digital video frame.

Abstract: A module installation assembly for installing a module into a socket of a land grid array includes a tool having a mounting bracket for connecting the tool to an adjacent fixture, an alignment member connected to the mounting bracket, and cavity defined at least partially by the alignment member. The cavity is substantially aligned with a socket of the land grid array such that the module is configured to pass through the cavity when being connected to the socket.

Abstract: A service identification method, a network entity and a user equipment using the same are provided. In one of the exemplary embodiments, this method is adapted to the network entity and includes at least but not limited to: receiving a broadcast service identifier allocation request; allocating at least one broadcast service identifier of at least one broadcast service in response to reception of the broadcast service identifier allocation request, wherein each of the at least one broadcast service identifier includes both of a service identification information and an area identification information, the service identification information is configure to identify the at least one broadcast service, and the area identification information is used to identify a target area corresponding to a broadcast service content of the broadcast service; and transmitting the at least one broadcast service identifier including the service identification information and the area identification information.

Abstract: A non-volatile memory (NVM) apparatus and an empty page detection method thereof are provided. The NVM apparatus includes a NVM and a controller. The controller reads the content of a memory page of the NVM. The controller performs Low Density Parity Check (LDPC) decoding for at least one codeword of the memory page to obtain a decoded codeword and a check-result vector. The controller determines that the memory page is not an empty page when the LDPC decoding for the codeword is successful. The controller counts an amount of the bits being 1 (or 0) in the check-result vector when the LDPC decoding for the codeword is fail. Based on the amount of the bits being 1 (or 0) in the check-result vector, the controller determines whether the memory page is an empty page.

Abstract: A system for capturing an eye diagram is disclosed.

Abstract: A method for comprehensively recovering rare earth elements and fluorine element in a bastnaesite treatment process. The method comprises: oxidation roasting a bastnaesite, and leaching a roasted mixture using a hydrochloric acid, adding a roasting promoter to the bastnaesite during the roasting process; and/or during the leaching process using the hydrochloric acid, adding a catalytic leaching promoter into the mixture, obtaining a rare earth chloride solution containing little cerium element and a cerium-rich residue containing the fluorine element; and separating and recovering rare earth fluorides from the cerium-rich residue.

Abstract: A system filters profiles of an online business network as a function of recent college graduates who have recently become employed in first employment positions, and identifies codes associated with the first employment positions. The system filters job listings using the identified codes to identify job listings that are closed and similar to the first employment positions. The system stores the identified job listings that are similar to the first employment positions into a first subset of job listings, and analyzes the job descriptions in the first subset of job listings using a logistic regression to model job listings with predictor variables indicating whether the requirements expressed in the job descriptions—for example, requirements of previous work experience—are likely optional or mandatory.

Abstract: A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has a first active region and a second active region. The first transistor includes a plurality of gate stacks disposed in the first active region. The second transistor includes a plurality of gate stacks disposed in the second active region. A ratio of the number of the gate stacks of the second transistor to an area size of the second active region is less than a ratio of the number of the gate stacks of the first transistor to an area size of the first active region.