Abstract: The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. Some implementations include a method of compressing a sequence of read data values into a bit-tuple of a predefined length to enable soft information decoding systems that use less power and/or less memory. In some implementations, the bit-tuple of a predefined length is produced using M single-bit buffer locations, where M corresponds to the predefined length of the bit-tuple. Some implementations utilize a collection of characterization vectors that include soft information values associated with the possible permutations of the bit-tuples. In turn, a sequence of bit-tuples is converted into a sequence of soft information values by retrieving a particular characterization vector, and selecting a respective soft information value from that characterization vector for each bit-tuple in the sequence.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance performance of error control encoding. The method includes receiving information data and generating parity information based on an m×k parity matrix comprising an array of b×b circulant sub-matrices, including m columns of said sub-matrices, each column comprising k said sub-matrices. The method further includes dividing the information data into a plurality of b-sized trunks and generating m parity segments. Each parity segment consists of b bits, and each parity segment is generated by multiplying each of the k b×b circulant sub-matrices in a respective column of the parity matrix by a corresponding trunk of information data, where each multiplication of a b×b circulant sub-matrix by a corresponding trunk comprises b2 concurrent computations. The method further includes generating a codeword based on the information data and the m parity segments.

Abstract: A method of making a stacked chip layout includes placing a first active circuit block over a central processing chip having a first area, the first active circuit block having a second area less than the first area. The method further includes placing a second active circuit block over the first active circuit block, the second active circuit block having a third area less than the first area, wherein the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The method further includes placing a third active circuit block over the second active circuit block wherein the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes at least a portion of the first and second active circuit blocks.

Abstract: A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.

Abstract: A quasi-cyclic low-density parity-check (QC-LDPC) encoder includes a Fourier transform circuit configured to receive an input message and to generate a transformed message based on the input message. The transformed message includes leading symbols with indices corresponding to leading elements of cyclotomic cosets of a finite field with respect to a subfield. The QC-LDPC encoder further includes a matrix multiplier circuit configured to multiply the leading symbols of the transformed message by leading symbols of a transformed LDPC generator matrix to generate leading symbols of transformed parity symbols associated with an LDPC codeword. The QC-LDPC encoder is configured to provide the leading symbols of the transformed parity symbols to an inverse Fourier transform circuit to generate parity information of the LDPC codeword.

Abstract: A low-density parity-check (LDPC) encoder is configured to encode data for storage into a non-volatile memory of a data storage device. The LDPC encoder includes a message mapping circuit configured to receive an input message and to generate a mapped message based on the input message. The LDPC encoder also includes a matrix multiplier circuit configured to multiply the mapped message with columns of a Fourier transform of an LDPC generator matrix to generate at least a portion of a transform of an LDPC codeword. The LDPC encoder is configured to provide the transform of the LDPC codeword to an inverse Fourier transform circuit to generate the LDPC codeword.

Abstract: A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

Abstract: A photo-electric device including a photoelectric conversion layer and a plurality of electrodes is provided. The photoelectric conversion layer includes a plurality of inversed pyramid shaped recesses and a plurality of a pyramids, wherein each of the inversed pyramid shaped recesses has at least three first reflection sidewalls, each of the pyramids is located in one of the inversed pyramid shaped recesses respectively, each of the pyramids has at least three second reflection sidewalls, and none of the first reflection sidewall and the second reflection sidewall is located in a same plane. The electrodes are electrically connected to the photoelectric conversion layer.

Abstract: A container, a nebulizer and a use of an indicator device are described, where the container comprises an indicator device fixedly mounted on the bottom of the container, the container is arranged within the nebulizer and the container can be detached by grabbing the indicator device.

Abstract: The invention relates to a device and a method for filtering a liquid sample, wherein first capillary-driven filtration occurs and, after initial filling, pressure-operated filtration is performed by applying a vacuum or a positive pressure.

Abstract: High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a first result of a first computation and a second result of a second computation. A length of a “critical path” of the decoder is reduced as compared to a critical path length in which a common feedback message is computed.

Abstract: Low complexity partial parallel architectures for performing a Fourier transform and an inverse Fourier transform over subfields of a finite field are described. For example, circuits to perform the Fourier transforms and the inverse Fourier transform as described herein may have architectures that have simplified multipliers and/or computational units as compared to traditional Fourier transform circuits and traditional inverse Fourier transform circuits that have partial parallel designs. In a particular embodiment, a method includes, in a data storage device including a controller and a non-volatile memory, the controller includes an inverse Fourier transform circuit having a first number of inputs coupled to multipliers, receiving elements of an input vector and providing the elements to the multipliers. The multipliers are configured to perform calculations associated with an inverse Fourier transform operation.

Abstract: A stacked chip layout includes a central processing chip has a first area and a first active circuit block over the central processing chip, the first active circuit block has a second area. The stacked chip layout further includes a second active circuit block over the first active circuit block, the second active circuit block has a third area, the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The stacked chip layout further includes a third active circuit block over the second active circuit block, the third active circuit block has a fourth area, the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes a portion of the first active circuit block and the second active circuit block.

Abstract: The various implementations described herein include systems, methods and/or devices for enhancing the performance of error control decoding. The method includes receiving at an LDPC decoder data from a storage medium corresponding to N variable nodes. The method further includes: updating a subset of the N variable nodes; updating all check nodes logically coupled to the updated subset of the N variable nodes; and generating check node output data for each updated check node including at least an updated syndrome check. Finally, the method includes: stopping decoding of the read data in accordance with a determination that the syndrome checks for all the M check nodes are valid syndrome checks or initiating performance of the set of operations with respect to a next subset of the N variable nodes in accordance with a determination that the syndrome checks for all the M check nodes include one invalid syndrome check.

Abstract: A method for comprehensively recovering rare earth elements and fluorine element in a bastnaesite treatment process. The method comprises: oxidation roasting a bastnaesite, and leaching a roasted mixture using a hydrochloric acid, adding a roasting promoter to the bastnaesite during the roasting process; and/or during the leaching process using the hydrochloric acid, adding a catalytic leaching promoter into the mixture, obtaining a rare earth chloride solution containing little cerium element and a cerium-rich residue containing the fluorine element; and separating and recovering rare earth fluorides from the cerium-rich residue.

Abstract: A method and a system for providing customizable, process-specific Just-In-Time debugging in operating system is provide in this invention. The method comprises the following steps: obtaining process-specific JIT debugging information, in response to the occurrence of an trap event in operating system; invoking the debugger corresponding to the process according to the obtained process-specific JIT debugging information. This method and system supports per-process JIT debugging configuration.

Abstract: A method and system for invoking Just-In-Time debugger is described, which can provide more efficient JIT debugging for complex code mixed applications. A method for invoking a Just-In-Time (JIT) debugger according to one embodiment includes checking a code type of a code address where a JIT debugging request is triggered from a process of a code-mixed application in response to the JIT debugging request from the process; acquiring corresponding JIT debugging information for different code types of the code-mixed application; and invoking a JIT debugger corresponding to the code type in response to the checked code type of the code address in the process and the acquired corresponding JIT debugging information.

Abstract: A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

Abstract: The invention relates to a method for washing at least one cavity (20?) in a microfluidic component, the cavity (20?) containing a first liquid (F1) and at least one second liquid (F2) being supplied to the cavity (20?) for washing. According to the invention an air bubble (L) is supplied to the cavity (20?) before the washing liquid (F2) is introduced. The air bubble (L), which acts as a virtual barrier layer between the first liquid (F1) and the washing liquid (F2) that follows it enables the washing efficiency to be increased considerably. Overall, this method leads to a saving in washing liquid (F2) and washing time. Moreover, a microfluidic component is proposed for carrying out the method.