Abstract: High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a first result of a first computation and a second result of a second computation. A length of a “critical path” of the decoder is reduced as compared to a critical path length in which a common feedback message is computed.

Abstract: A device is disclosed that includes a driver circuit and a control circuit. The driver circuit is configured to provide an output signal according to an input signal, and operated with a first voltage and a second voltage. The driver circuit includes a pull up unit and a pull down unit configured to pull up and pull down a voltage level of the output signal, respectively. The control circuit is configured to selectively enable one of the pull up unit and the pull down unit according to the input signal, so as to adjust the voltage level of the output signal. The control circuit is further configured to drive the enabled one of the pull up unit and the pull down unit in a voltage mode or a current mode selectively according to the voltage level of the output signal, the first voltage and the second voltage.

Abstract: A stacked chip layout includes a central processing chip; and a first active circuit block over the central processing chip. The stacked chip layout further includes a second active circuit block over the first active circuit. A center of the second active circuit block is offset from a center of the first active circuit block, the second active circuit block overlaps the first active circuit block in a partial overlap area, and the second active circuit block exposes a portion of the first active circuit block. The stacked chip layout further includes a local conductive element electrically connecting the first active circuit block to the second active circuit block. The local conductive element is within the partial overlap area.

Abstract: Systems and methods for managing overlapping taxonomies, in accordance with some embodiments, are disclosed. The system stories a set of taxonomic grouping rules for organizing members based on stored member data and receives a request for grouping information for a particular member. Using stored member data for the particular member, the system classifies the particular member into an atomic taxonomic group in the plurality of the atomic taxonomic groups. The system, based on the atomic taxonomic group that the particular member is classified into, automatically determines the requested grouping information. The system then transmits the requested grouping information to a requesting computer system.

Abstract: Thermal recovery method via electrically heating edge- and bottom-water layer by horizontal wells is presented. Edge- and bottom-water layer is electrically heated by using a plurality of horizontal wells that are located at the upper part of edge- and bottom-water layer, so that the temperature of the whole oil deposit is increased to a state in which in-place oil can flow, by using the theory of centralized heat supply to improve the thermal recovery efficiency. Also disclosed is an electric heating structure for a horizontal well. The electric heating structure is provided with a sieve pipe. A plurality of ferromagnetic permanent magnets is deployed at the upper part of the inner side of the sieve pipe. Spring-shaped electric heating rods serially connected together are disposed in the middle. A heat separation board is disposed in the position of a horizontal diameter.

Abstract: A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal.

Abstract: A method of making a stacked chip layout includes placing a first active circuit block over a central processing chip having a first area, the first active circuit block having a second area less than the first area. The method further includes placing a second active circuit block over the first active circuit block, the second active circuit block having a third area less than the first area, wherein the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The method further includes placing a third active circuit block over the second active circuit block wherein the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes at least a portion of the first and second active circuit blocks.

Abstract: Network insights are bite-sized pieces of information about member's connections in the on-line social network that contain information that may be of interest to a viewing member but that is difficult or time-consuming to find. A network insights system generates and stores insights for each member in an on-line social network system. A network insights system also generates a set of personalization features for each member profile in the on-line social network. A set of personalization features for a member profile reflects the relevance of each possible value of a certain profile attribute with respect to the member profile. When a network insights system determines that a member (the viewer) is to be presented with one or more insights with respect to another member (the viewee) it selects insights of the viewee for presentation to the viewer based on the set of personalization features for the viewer.

Abstract: A device is disclosed that includes a driver circuit and a control circuit. The driver circuit is configured to provide an output signal according to an input signal, and operated with a first voltage and a second voltage. The driver circuit includes a pull up unit and a pull down unit configured to pull up and pull down a voltage level of the output signal, respectively. The control circuit is configured to selectively enable one of the pull up unit and the pull down unit according to the input signal, so as to adjust the voltage level of the output signal. The control circuit is further configured to drive the enabled one of the pull up unit and the pull down unit in a voltage mode or a current mode selectively according to the voltage level of the output signal, the first voltage and the second voltage.

Abstract: A method is provided that includes performing first decoding operations on data obtained from a plurality of units of memory using soft information values for the plurality of units of memory, where the plurality of units of memory includes an error correction stripe. The method further includes determining that two or more units of memory have uncorrectable errors. The method further includes updating a soft information value for a first unit of memory in accordance with a magnitude of a soft information value for a second unit and a direction based on parity of the error correction stripe excluding the first unit, where the first unit of memory and the second unit of memory are included in the two or more units of memory that have uncorrectable errors. The method further includes performing a second decoding operation on data obtained from the first unit using the updated soft information value.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. The method includes, in response to one or more host read commands, reading data from a set of memory cells in a flash memory array in accordance with a first reading threshold voltage and performing an error correction process on the read data to produce error correction information. The method further includes determining, based on the error correction information, whether to adjust the first reading threshold voltage, and upon determining to adjust the first reading threshold voltage, setting the value of the first reading threshold voltage to a value greater or less than a current value of the first reading threshold voltage. In some implementations, the method further includes initiating a recalibration of the first reading threshold voltage when a predefined condition occurs.

Abstract: Systems, methods, and/or devices are used to improve decoding of data read from a storage device with one or more memory devices. In one aspect, the method includes obtaining, in response to a read request, a codeword with two or more codeword portions from distinct memory portions of the storage device. When a decoding iteration on the codeword fails to satisfy predetermined decoding criteria, the method includes, for the two or more codeword portions of the codeword: determining a bit-flip count between raw read data for a respective codeword portion and a decoding result for the respective codeword portion after the decoding iteration; determining a soft information offset for the respective codeword portion based on the bit-flip count for the respective codeword portion relative to bit-flips counts for other codeword portions; and adjusting soft information for the respective codeword portion based on the soft information offset.

Abstract: Among other things, one or more techniques and systems for performing design layout are provided. An initial design layout is associated with an electrical component, such as a standard cell. A conflict graph is generated based upon the initial design layout. The conflict graph comprises one or more nodes, representing polygons within the initial design layout, connected by one or more edges. A same-process edge specifies that two nodes are to be generated by the same pattern process, while a different-process edge specified that two nodes are to be generated by different pattern processes, such as a mandrel pattern process and a passive fill pattern process. The conflict graph is evaluated to identify a conflict, such as a self-aligned multiple pattering (SAMP) conflict, associated with the initial design layout. The conflict is visually displayed so that the initial design layout can be modified to resolve the conflict.

Abstract: A low-density parity-check (LDPC) encoder is configured to encode data for storage into a non-volatile memory of a data storage device. The LDPC encoder includes a message mapping circuit configured to receive an input message and to generate a mapped message based on the input message. The LDPC encoder also includes a matrix multiplier circuit configured to multiply the mapped message with columns of a Fourier transform of an LDPC generator matrix to generate at least a portion of a transform of an LDPC codeword. The LDPC encoder is configured to provide the transform of the LDPC codeword to an inverse Fourier transform circuit to generate the LDPC codeword.

Abstract: The invention provides a delivery system comprising a cell penetrating peptide, 10 histidines, and an interfering RNA molecule. The system can be used for delivering interfering RNA molecules into a cell in vivo or in vitro. Therapeutic uses for the delivery system are also provided.

Abstract: A semiconductor device for simultaneous operation at two temperature ranges includes a substrate, a first transistor, and a second transistor. The substrate has a first active region and a second active region. The first transistor includes a plurality of gate stacks disposed in the first active region. The second transistor includes a plurality of gate stacks disposed in the second active region. A ratio of the number of the gate stacks of the second transistor to an area size of the second active region is less than a ratio of the number of the gate stacks of the first transistor to an area size of the first active region.

Abstract: A quasi-cyclic low-density parity-check (QC-LDPC) encoder includes a Fourier transform circuit configured to receive an input message and to generate a transformed message based on the input message. The transformed message includes leading symbols with indices corresponding to leading elements of cyclotomic cosets of a finite field with respect to a subfield. The QC-LDPC encoder further includes a matrix multiplier circuit configured to multiply the leading symbols of the transformed message by leading symbols of a transformed LDPC generator matrix to generate leading symbols of transformed parity symbols associated with an LDPC codeword. The QC-LDPC encoder is configured to provide the leading symbols of the transformed parity symbols to an inverse Fourier transform circuit to generate parity information of the LDPC codeword.

Abstract: A circuit comprises a voltage supply node, a reference voltage node, and a plurality of transistors coupled with the voltage supply node and the reference voltage node. The circuit also comprises a circuit input, a first delay element and a second delay element. The first delay element is coupled with the circuit input and one transistor of the plurality of transistors. The second delay element is coupled with the circuit input and a second transistor of the plurality of transistors. The circuit further comprises a circuit output coupled with the first transistor of the plurality of transistors and the second transistor of the plurality of transistors. The circuit additionally comprises a bias generator coupled with the circuit output, the first transistor of the plurality of transistors and the second transistor of the plurality of transistors.

Abstract: A circuit comprises a voltage supply node, a reference voltage node, and a plurality of transistors coupled with the voltage supply node and the reference voltage node. The circuit also comprises a circuit input, a first delay element and a second delay element. The first delay element is coupled with the circuit input and one transistor of the plurality of transistors. The second delay element is coupled with the circuit input and a second transistor of the plurality of transistors. The circuit further comprises a circuit output coupled with the first transistor of the plurality of transistors and the second transistor of the plurality of transistors. The circuit additionally comprises a bias generator coupled with the circuit output, the first transistor of the plurality of transistors and the second transistor of the plurality of transistors.

Abstract: In a method for filtering messages being executed by at least one processor of electronic devices, the method includes detecting a message filtering template set by the first electronic device when the first electronic logs into the server successfully; sends a content of the message filtering template and a communication request from the first electronic device to the server; sends the content to the second electronic device by the server, the content of the message filtering template including functions of stop receiving messages from group members within a first certain period of time or refusing to send messages to one or more group members within a second certain period of time; and receiving a selection from the second electronic device through the server.