Abstract: A method implemented by a network topology design system, the network topology design system including a processing device. The method to determine placement of a controller within a network with a split architecture where control plane components of the split architecture network are executed by a controller and the control plane components are separate from data plane components of the split architecture network. The placement of the controller is selected to minimize disruption of the split architecture network caused by a link failure, a switch failure or a connectivity loss between the controller and the data plane components.

Abstract: A computing device determines an optimal allocation of network bandwidth on a plurality of communications links for a plurality of virtual machines (VMs) in a multi-tenant cloud network based upon a set of bandwidth requirements for the plurality of VMs. The computing device generates a plurality of spanning tree data structures (TDSs). Edges in the TDSs include computed bandwidth values indicating an amount of bandwidth to be reserved over a communications link represented by that edge for the plurality of VMs. The computing device generates a weighted distance value for each TDS of the plurality of TDSs, and selects a TDS of the plurality of TDSs having a smallest weighted distance value as the TDS having computed bandwidth values representing the optimal allocation of network bandwidth.

Abstract: A method for localized congestion exposure within a local loop in a cellular network that is performed by a localized congestion exposure receiver node of the local loop. The method includes receiving downlink packets destined for a downstream user device. The downlink packets have headers that indicate a level of congestion experienced by the downlink packets. The headers also indicate a level of expected downstream congestion declared by an upstream node. The method also includes forwarding the downlink packets to the downstream user device through a wireless connection. The method further includes sending packets upstream that have feedback indicative of the level of congestion experienced by the downlink packets and any congestion experienced within the localized congestion exposure receiver node.

Abstract: A method implemented by a network topology design system, the network topology design system including a processing device. The method to determine placement of a controller within a network with a split architecture where control plane components of the split architecture network are executed by a controller and the control plane components are separate from data plane components of the split architecture network. The placement of the controller is selected to minimize disruption of the split architecture network caused by a link failure, a switch failure or a connectivity loss between the controller and the data plane components.

Abstract: A method for placing services at network devices is disclosed. A network contains a plurality of network devices and the network offers a set of services to subscribers. Each subscriber of the network utilizes a subset of the set of service, where an order of the services is not predefined. The method starts with ordering the services from the most utilized service to the least utilized, and selects services from the most utilized to the least utilized. For each service, a network device is selected so that placing the service adds a least sum of additional delay based on services already placed in the network, and a path for each subscriber utilizing the service is updated to include the service, where the path is an ordered chain of services, and where the service is inserted in the path to result in minimum addition to delay to the subscriber.

Abstract: A method of manufacturing an article includes providing a component for an etch reactor. Ion beam sputtering with ion assisted deposition (IBS-IAD) is then performed to deposit a protective layer on at least one surface of the component, wherein the protective layer is a plasma resistant film having a thickness of less than 1000 ?m.

Abstract: Methods for fabricating a nanopillared substrate surface include applying a polymer solution containing an amphiphilic block copolymer and a hydrophilic homopolymer to a substrate surface. The amphiphilic block copolymer and the hydrophilic homopolymer in the polymer solution self-assemble on the substrate surface to form a self-assembled polymer layer having hydrophobic domains adjacent to the substrate surface and hydrophilic domains extending into the self-assembled polymer layer. At least a portion of the hydrophilic domains may be removed to form a plurality of pores in the exposed surface of the self-assembled polymer layer. A protective layer may be deposited on the exposed surface as a mask for etching through the plurality of pores to form through-holes. A nanopillar-forming material may be deposited onto the substrate surface via the through-holes. Then, the remaining portion of the self-assembled polymer layer may be removed to expose a nanopillared substrate surface.

Abstract: Semiconductor light converting constructions are disclosed. The semiconductor light converting construction includes a first semiconductor layer for absorbing at least a portion of light at a first wavelength; a semiconductor potential well for converting at least a portion of the light absorbed at the first wavelength to light at a longer second wavelength; and a second semiconductor layer that is capable of absorbing at least a portion of light at the first wavelength. The first semiconductor layer has a maximum first index of refraction at the second wavelength. The second semiconductor layer has a second index of refraction at the second wavelength that is greater than the maximum first index of refraction.

Abstract: A method of localized congestion exposure within a local loop in a cellular network that is performed by a localized congestion exposure sender node of the local loop. The method includes receiving downlink packets that are destined for a downstream user device. The method also includes receiving packets that have feedback indicating a congestion level from a downstream node of the cellular network. The method further includes inserting a declaration of an expected downstream congestion level into headers of the received downlink packets; and forwarding the downlink packets that have the declaration of the expected downstream congestion level inserted into the headers toward the downstream user device.

Abstract: The present invention relates to a metal silicoaluminophosphate molecular sieve MeAPSO with a RHO framework structure and a preparation method thereof. The metal silicoaluminophosphate molecular sieve is characterized in that: the metal atoms are at least one of vanadium, copper, molybdenum, zirconium, cobalt, manganese, magnesium, iron, nickel and zinc. The chemical composition of said metal silicoaluminophosphate molecular sieve in anhydrous state is expressed as: mR.nMe.(SixAlyPz)O2, where R represents template existed in molecular sieve micropores, m is the molar number of said template per one molar of (SixAlyPz)O2, m=0.1˜0.5; Me represents metal atom entering into said metal silicoaluminophosphate molecular sieve framework, n is the molar number of Me per one molar of (SixAlyPz)O2, n=0.001˜0.30. Said metal silicoaluminophosphate molecular sieve has ion exchange performance and adsorption performance.

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a trench defining a mandrel structure. Sidewalls of the mandrel structure and a bottom surface of the trench are oxidized and subsequently etched to reduce a width of the mandrel structure. The oxidation and etching of the mandrel structure may be repeated until a desired width of the mandrel structure is achieved. A semiconducting material is subsequently deposited on a regrowth region of the mandrel structure to form a fin structure. The oxidizing and etching the mandrel structure provides a method for forming the fin structure which can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract: Etched substrates, and particularly, light-absorbing etched substrates, and methods for making such substrates are described.

Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

Abstract: Disclosed is a process for hydrotreating inferior naphtha fraction, comprising: (1) warming a recycle oil in a heating device; (2) mixing the inferior naphtha fraction with the recycle oil before and/or after the heating device; and (3) feeding the mixture of the inferior naphtha fraction and the recycle oil into a separating unit, wherein the gas-liquid separation is realized at least to obtain a gas phase and a liquid phase, wherein the gas phase comprises gasified inferior naphtha, wherein the gas phase enters a hydrotreating reactor to undergo hydrotreating, and wherein part of the liquid phase circulates to the heating device as the recycle oil; wherein warming of the recycle oil is controlled to ensure the temperature of gas phase from the separator at least reaches the inlet temperature of the hydrotreating reactor. Comparing with the prior art, the inventive process effectively solves the coking problem of the hydrogenating unit for inferior naphtha fraction.

Abstract: A gas comprising oxygen is supplied to a plasma source. A plasma jet comprising oxygen plasma particles is generated from the gas. A contaminant is removed from the component using the oxygen plasma particles.

Abstract: A network element controls congestion in a link of a packet data network. A congested link is identified and a throttle rate is determined for one or more of the traffic groups traversing the congested link. The central controller determines the throttle rates using a weight of the group and the current traffic rate of the group through the link. The throttle rates are sent to switches to throttle traffic for each affected group.

Abstract: The present invention relates to the technical field of communications. Disclosed are a method and device for downlink data transmission for use in reducing network resource wastage when a network side is transmitting data to a certain group of user terminals, thus increasing network resource utilization rate. The method comprises: grouping specific user terminals into a group, and identifying each group with a unique Group ID; a user terminal, when idle, monitors paging messages intended for it, and a first message; when a network side is transmitting downlink data, the network side transmits downlink data transmission scheduling information, and pages the group of user terminals at a timing of the group by means of the first message carrying the Group ID of the group; the user terminals that have received the first message receive the downlink data at a time window and a fixed physical resource position on the basis of the group-based downlink data transmission scheduling information received.

Abstract: A method for fabricating recessed source and recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the source and the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed source region; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps may be performed on a substrate to provide a trench over which a dielectric layer is conformally deposited. The dielectric layer is subsequently etched within the trench to expose the underlying substrate and a semiconductive material is deposited in the trench to form a fin structure. The processes of forming the trench, depositing the dielectric layer, and forming the fin structure can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.

Abstract: A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure.