Abstract: A Field Effect Transistor device includes a buried oxide layer, a silicon layer above the buried oxide layer, an isotropically recessed source region, and a gate stack comprising a gate dielectric, a conductive material, and a spacer.

Abstract: A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively.

Abstract: A method implemented by a network topology design system, the network topology design system including a processing device. The method to determine placement of a controller within a network with a split architecture where control plane components of the split architecture network are executed by a controller and the control plane components are separate from data plane components of the split architecture network. The placement of the controller is selected to minimize disruption of the split architecture network caused by a link failure, a switch failure or a connectivity loss between the controller and the data plane components.

Abstract: An embodiment method of controlling threshold voltages in a fin field effect transistor (FinFET) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.

Abstract: A method implemented by a network topology design system, the network topology design system including a processing device. The method to determine placement of a controller within a network with a split architecture where control plane components of the split architecture network are executed by a controller and the control plane components are separate from data plane components of the split architecture network. The placement of the controller is selected to minimize disruption of the split architecture network caused by a link failure, a switch failure or a connectivity loss between the controller and the data plane components.

Abstract: Compounds active on c-kit protein kinases or mutant c-kit protein kinases having any mutations are described, as well as methods of making and using such compounds to treat diseases and conditions associated with aberrant activity of the c-kit protein kinases and/or mutant c-kit protein kinases.

Abstract: Methods for replicating a nanopillared surface include applying a nanopillar-forming material to a surface of a replica substrate to form a precursor layer on the replica-substrate surface. A template surface of a nanomask may be contacted to the precursor layer. The nanomask may include a self-assembled polymer layer on a nanomask-substrate surface, the template surface being defined in the self-assembled polymer layer. The self-assembled polymer layer may have nano-sized pores with openings at the template surface. The precursor layer may be cured while the template surface remains in contact with the precursor layer. The nanomask is removed to expose a nanopillared surface having a plurality of nanopillars on the replica-substrate surface. The nanopillars on the replica-substrate surface may correspond to the pores in the template surface. Nanopillared surfaces may be replicated on one side of the replica substrate or on two opposing sides of the replica substrate.

Abstract: Methods for fabricating a nanopillared substrate surface include applying a polymer solution containing an amphiphilic block copolymer and a hydrophilic homopolymer to a substrate surface. The amphiphilic block copolymer and the hydrophilic homopolymer in the polymer solution self-assemble on the substrate surface to form a self-assembled polymer layer having hydrophobic domains adjacent to the substrate surface and hydrophilic domains extending into the self-assembled polymer layer. At least a portion of the hydrophilic domains may be removed to form a plurality of pores in the exposed surface of the self-assembled polymer layer. A protective layer may be deposited on the exposed surface as a mask for etching through the plurality of pores to form through-holes. A nanopillar-forming material may be deposited onto the substrate surface via the through-holes. Then, the remaining portion of the self-assembled polymer layer may be removed to expose a nanopillared substrate surface.

Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

Abstract: Material comprising sub-micrometer particles dispersed in a polymeric matrix. The materials are useful in article, for example, for numerous applications including display applications (e.g., liquid crystal displays (LCD), light emitting diode (LED) displays, or plasma displays); light extraction; electromagnetic interference (EMI) shielding, ophthalmic lenses; face shielding lenses or films; window films; antireflection for construction applications; and construction applications or traffic signs.

Abstract: A material can be locally etched with arbitrary changes in the direction of the etch. A ferromagnetic-material-including catalytic particle is employed to etch the material. A wet etch chemical or a plasma condition can be employed in conjunction with the ferromagnetic-material-including catalytic particle to etch a material through a catalytic reaction between the catalytic particle and the material. During a catalytic etch process, a magnetic field is applied to the ferromagnetic-material-including catalytic particle to direct the movement of the particle to any direction, which is chosen so as to form a contiguous cavity having at least two cavity portions having different directions. The direction of the magnetic field can be controlled so as to form the contiguous cavity in a preplanned pattern, and each segment of the contiguous cavity can extend along an arbitrary direction.

Abstract: A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively.

Abstract: A method includes forming a gate stack to cover a middle portion of a semiconductor fin, and doping an exposed portion of the semiconductor fin with an n-type impurity to form an n-type doped region. At least a portion of the middle portion is protected by the gate stack from receiving the n-type impurity. The method further includes etching the n-type doped region using chlorine radicals to form a recess, and performing an epitaxy to re-grow a semiconductor region in the recess.

Abstract: A process for etching semiconductors, such as II-VI or III-V semiconductors is provided. The method includes sputter etching the semiconductor through an etching mask using a nonreactive gas, removing the semiconductor and cleaning the chamber with a reactive gas. The etching mask includes a photoresist. Using this method, light-emitting diodes with light extracting elements or nano/micro-structures etched into the semiconductor material can be fabricated.

Abstract: A fair weighted-hashing technique may be used in load balancing among a group of modules. In one implementation, a device may maintain a table that relates how incoming client resource requests are to be distributed among the modules. The device may update the table, in response to an indication that an additional module, associated with a module identifier, is to be included in the group of modules. The updating may include determining a number of entries to add to the table for the additional module, calculating a first hash value for each of the number of entries, and modifying the table by writing the module identifier to one or more sequential entries of the table, beginning at an index into the table corresponding to the first hash value.

Abstract: A method for implementing a general packet radio service (GPRS) tunnel protocol (GTP) in a packet core (PC) of a third generation (3G) network having a split architecture where a control plane of the PC of the 3G network is in a cloud computing system, the cloud computing system including a controller, the controller to execute a plurality of control plane modules, the control plane to communicate with the data plane of the PC through a control plane protocol, the data plane implemented in a plurality of network elements of the 3G network by configuring switches implementing a data plane of the SGSN and GGSN and intermediate switches to establish a first and second GTP tunnel endpoint.

Abstract: Techniques for fabricating nanowire/microwire-based solar cells are provided. In one, a method for fabricating a solar cell is provided. The method includes the following steps. A doped substrate is provided. A monolayer of spheres is deposited onto the substrate. The spheres include nanospheres, microspheres or a combination thereof. The spheres are trimmed to introduce space between individual spheres in the monolayer. The trimmed spheres are used as a mask to pattern wires in the substrate. The wires include nanowires, microwires or a combination thereof. A doped emitter layer is formed on the patterned wires. A top contact electrode is deposited over the emitter layer. A bottom contact electrode is deposited on a side of the substrate opposite the wires.

Abstract: A lenticular system for autostereoscopic display devices in which a transparent polymeric lenticular array is embedded between two glass sheets and the gap between the polymeric lenticular array and the outer cover is filled with a transparent polymeric filling having a refractive index different than the refractive index of the polymeric lenticular array to reduce glare.

Abstract: Mouse monoclonal antibodies specifically recognizing the Penicillin Binding Protein 2a (PBP2a) derived from a strain of Methicillin-Resistant Staphylococcus aureus (MRSA) were produced and characterized. The immunogen used to generate an immune response in a mouse was a PBP2a recombinant protein derived from a strain of Methicillin-Resistant Staphylococcus aureus (MRSA). The data showed that both monoclonal antibodies of the disclosure were able to distinguish MRSA from MSSA bacteria. The monoclonal antibodies have distinct recognition patterns for the regions of the PBP2a protein sequence. Epitope mapping has localized regions of the PBP2a protein specifically recognized by one or both of the monoclonal antibodies. The monoclonal antibodies of the present disclosure having the ability to distinguish between MRSA and MSSA strains can be useful as the basis for a diagnostic assay useful in the clinical setting for determining whether and which antibiotics to administer to a patient.