Abstract: A system includes memory chips mounted on a memory module each having an alert terminal that notifies that the memory chip has detected a predetermined error. The memory module has a first transmission line connected to alert terminals of memory chips, output terminal being connected to one end of the first transmission line, and a first termination resistor having an end connected to another end of the first transmission line. The system further includes a second transmission line having an end connected to the alert terminal and another end connected to a controller and a third transmission line having an end connected to a first input terminal on the memory module and a second end line and a second end having a voltage different from a voltage of another end of the first termination resistor.

Abstract: A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices, and a plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other.

Abstract: Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line.

Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

Abstract: A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.

Abstract: A plurality of memory chips each have an alert terminal that notifies the outside that the memory chip has detected a predetermined error. The plurality of memory chips are mounted on memory module 100. Memory module 100 has a first transmission line connected to an alert terminal of each of the plurality of memory chips, output terminal 101 being connected to one end of the first transmission line, and a first termination resistor being connected to another end of the first transmission line.

Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.

Abstract: The semiconductor device includes an output driver and a characteristic switching circuit that switches characteristics of the output driver. The characteristic switching circuit mutually matches a rising time and a falling time of an output signal output from the output driver, when a power voltage supplied to a power line is a first voltage, with a rising time and a falling time of the output signal output from the output driver, when the power voltage supplied to the power line is a second voltage. As a result, an increase in an influence of a harmonic component or a crosstalk when the power voltage is reduced does not occur. Moreover, because a receiving condition on a receiver side does not change even when the power voltage is reduced, signal transmission and reception can be performed correctly irrespective of the power voltage.

Abstract: A control device that comprises a first data strobe input terminal to be connected in common to data strobe terminals that are included respectively in first memory devices, and a plurality of first sub-units each coupled to the first data strobe input terminal and each holding a data strobe delay value corresponding to an associated one of the first memory devices, and the data strobe delay values of the sub-units being independent from each other.

Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.

Abstract: A memory buffer mounted on a memory module includes a pre-launch function of advancing outputs of address/command signal and a post-launch function of delaying outputs of control signal. A time step increment for pre/post-launch time adjustment is set to be equal to or finer than tCK/32 where tCK is one clock cycle.

Abstract: Disclosed herein is a device that includes a plurality of semiconductor chips mounted on a module substrate. Each of the semiconductor chips includes a reset terminal to which a reset signal is supplied, and an internal circuit that is initialized based on the reset signal. The module substrate includes a reset signal line connected commonly to the reset terminals of the semiconductor chips, and an anti-resonance element connected to the reset signal line.

Abstract: A plurality of vias is disposed side by side on a multilayer board. A first via which is one of the vias disposed at one outer portion is electrically connected to a first outgoing line provided on the multilayer board. A second via at the other outer portion is electrically connected to a second outgoing line provided on the multilayer board. A plurality of the vias is connected to a first fixed potential layer (a ground layer, for example) of the multilayer board. At least one second fixed potential layer is provided, with a plurality of the vias through a clearance and having the same potential as that of the first fixed potential layer, as an inner layer of the multilayer board between the first and second outgoing lines and the fixed potential layer. Therefore, a BPF whose rate of occupied area is low is formed on the multilayer board without additional production processes.

Abstract: A method for extracting an accurate IBIS simulation model of a semiconductor device including a plurality of semiconductor chips comprises: extracting an AC characteristics model of a first output buffer in an IBIS simulation model by treating first and second output buffers of first and second semiconductor chips connected to a single external connection terminal as a transistor model and executing a transistor-level circuit simulation; calculating an output capacitance model of the first output buffer as an IBIS simulation model by adding output capacitances of the first and second output buffers as a transistor-level circuit simulation model; and synthesizing an IBIS simulation model of the first output buffer viewed from the external connection terminal by using the AC characteristics model and the output capacitance model.

Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

Abstract: In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.

Abstract: A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 ?m therebetween.

Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.