Abstract: There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.

Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

Abstract: A memory module includes at least one CAR and a plurality of DRAMs provided so as to be close and adjacent to one another on one face and the other face of a module substrate. The DRAMs are divided into a plurality of memory groups. Memory groups adjacent to each other of these memory groups are paired with each other. One of this pair is a 1-ranked memory group and the other is a 2-ranked memory group. This pair of the memory groups is connected to the CAR via short wiring with a T-branch structure having a short stub. One of the pair of the memory groups on the signal-reception side functions as an open end. Active termination is performed by a termination resistor of the other of the pair of the memory groups on the signal-non-reception side. Subsequently, signal reflections can be reduced.

Abstract: A point-to-point bus and a daisy chain bus are provided for supplying signals to stacked memories, and the stacked memories are mounted mutually apart by a distance equivalent to the length of the stacked memory on both surfaces of a module substrate. Furthermore, the memory chips arranged in a stacked memory mounted on one surface are set in an active state at the same time alternately with the memory chips arranged in a stacked memory mounted on another surface of the module substrate.

Abstract: Each of stacked memory chips has an ID generator circuit for generating identification information in accordance with its manufacturing process. Since the memory chip manufacturing process implies process variations, the IDs generated by the respective ID generator circuits are different from one another even though the ID generator circuits are identical in design. A memory controller instructs an ID detector circuit to detect the IDs of the respective memory chips, and individually controls the respective memory chips based on the detected IDs.

Abstract: A memory module of the unbuffered type with ECC function is employed. Configuration of an internal C/A bus is set to a single T-branch topology. An output impedance of a chipset is maintained substantially constant. A capacitor for cutting high-frequency components of a C/A signal is added on a C/A bus.

Abstract: The present invention provides a semiconductor apparatus including an internal clock generating unit and a data storing unit. The internal clock generating unit generates an internal clock signal based on an external clock signal and a clock control signal. The data storing unit which operates data processing based on the internal clock signal. The internal clock generating unit carries out synchronous control such that the internal clock signal is synchronized with the external clock signal. The data storing unit generates the clock control signal based on the data processing and outputs the clock control signal to the internal clock generating unit to control the synchronous control. The data storing unit may controls the internal clock generating unit such that the synchronous control is adjourned or restrained temporarily while the data processing is a data reading process.

Abstract: Semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected by a bidirectional bus which is a transmission line. A driver is of a push-pull type and a reception side is CTT-terminated. If a terminating resistor is in conformity with the characteristic impedance of the transmission line, the on resistance of the driver is equal to or lower than the characteristic impedance. If the on resistance of the driver is in conformity with the characteristic impedance of the transmission line, the value of the terminating resistor is equal to or lower than the characteristic impedance of the transmission line. If the reception side is VTT-terminated, the value of the VTT is {fraction (1/2)} of a lower one of power supply voltages that are supplied to the respective semiconductor integrated circuit devices. The value of the terminating resistor is in conformity with the characteristic impedance of the transmission line.

Abstract: A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.

Abstract: A process for producing a sealed container from a tubular blank of square cross section by folding and sealing a container bottom forming portion of the blank to form a flat bottom includes the step of sealing the bottom by collapsing an opening edge part of the container bottom forming portion to a flat form and sealing opposed walls of the collapsed opening edge part as lapped over each other to form a straight bottom seal rib.

Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

Abstract: First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

Abstract: A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus.

Abstract: The present invention provides a semiconductor apparatus including an internal clock generating unit and a data storing unit. The internal clock generating unit generates an internal clock signal based on an external clock signal and a clock control signal. The data storing unit which operates data processing based on the internal clock signal. The internal clock generating unit carries out synchronous control such that the internal clock signal is synchronized with the external clock signal. The data storing unit generates the clock control signal based on the data processing and outputs the clock control signal to the internal clock generating unit to control the synchronous control. The data storing unit may controls the internal clock generating unit such that the synchronous control is adjourned or restrained temporarily while the data processing is a data reading process.

Abstract: A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.

Abstract: In a multilayer interconnection layer of a mother board and a memory module, a position relationship between a bus interconnection layer and a conductive layer of a power supply layer or a ground layer opposite to the bus interconnection layer is substantially held in not only the mother board but also the memory module and a relationship of multilayer interconnections is unified. As a result, it is possible to reduce disturbance of a return current of a high frequency signal given to the bus interconnection layer, to prevent degradation of quality of a signal waveform caused by the disturbance of the return current, and to prevent unnecessary electromagnetic waves from radiating caused by the disturbance of the return current.

Abstract: A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

Abstract: Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register.

Abstract: A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

Abstract: A liquid metering and filling lifter for use with different kinds of containers (C) having different heights for moving the container (C) upward and downward with a stroke corresponding to the height of the container (C) in filling a liquid into the container, the lifter comprising a container pushing-up vertical lift rod (32) disposed below a filling nozzle (13) above a bed (11) and extending through the bed (11), the lift rod (32) having a container support (31) fixed to an upper end thereof, a container pushing-down vertical lift rod (34) extending through the bed (11) at one side of the lift rod (32) and having a container holder (33) fixed to an upper end thereof, and coupling means (35) disposed below the bed (11) for coupling the two lift rods (32), (34) to make the lift rods movable upward or downward together and uncoupling the lift rods (32), (34) to make the lift rods movable upward or downward individually.