Abstract: A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.

Abstract: A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

Abstract: A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.

Abstract: The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

Abstract: A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.

Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

Abstract: A point-to-point bus and a daisy chain bus are provided for supplying signals to stacked memories, and the stacked memories are mounted mutually apart by a distance equivalent to the length of the stacked memory on both surfaces of a module substrate. Furthermore, the memory chips arranged in a stacked memory mounted on one surface are set in an active state at the same time alternately with the memory chips arranged in a stacked memory mounted on another surface of the module substrate.

Abstract: There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.

Abstract: In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.

Abstract: Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register.

Abstract: A memory module comprises a stab resistor between a pin and one end of a bus. A plurality of memory chips is connected to the bus between both ends thereof. A terminating resistor is connected to the other end of the bus. Stab resistance Rs of the stab resistor and terminating resistance Rterm of the terminating resistor are given by: Rs=(N?1)×Zeffdimm/N, and Rterm=Zeffdimm where N represents the number of the memory modules in a memory system; and Zeffdimm, effective impedance of a memory chip arrangement portion consisting of the bus and the memory chips. In the memory system, the memory modules are connected to a memory controller on a motherboard in a stab connection style. Wiring impedance Zmb of the motherboard is given by: Zmb=(2N?1)×Zeffdimm/N2.

Abstract: The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract: A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.

Abstract: Semiconductor integrated circuit devices that operate under different power supply voltages are directly interconnected by a bidirectional bus which is a transmission line. A driver is of a push-pull type and a reception side is CTT-terminated. If a terminating resistor is in conformity with the characteristic impedance of the transmission line, the on resistance of the driver is equal to or lower than the characteristic impedance. If the on resistance of the driver is in conformity with the characteristic impedance of the transmission line, the value of the terminating resistor is equal to or lower than the characteristic impedance of the transmission line. If the reception side is VTT-terminated, the value of the VTT is ½ of a lower one of power supply voltages that are supplied to the respective semiconductor integrated circuit devices. The value of the terminating resistor is in conformity with the characteristic impedance of the transmission line.

Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

Abstract: In a multilayer interconnection layer of a mother board and a memory module, a position relationship between a bus interconnection layer and a conductive layer of a power supply layer or a ground layer opposite to the bus interconnection layer is substantially held in not only the mother board but also the memory module and a relationship of multilayer interconnections is unified. As a result, it is possible to reduce disturbance of a return current of a high frequency signal given to the bus interconnection layer, to prevent degradation of quality of a signal waveform caused by the disturbance of the return current, and to prevent unnecessary electromagnetic waves from radiating caused by the disturbance of the return current.

Abstract: In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.

Abstract: A memory module includes at least one CAR and a plurality of DRAMs provided so as to be close and adjacent to one another on one face and the other face of a module substrate. The DRAMs are divided into a plurality of memory groups. Memory groups adjacent to each other of these memory groups are paired with each other. One of this pair is a 1-ranked memory group and the other is a 2-ranked memory group. This pair of the memory groups is connected to the CAR via short wiring with a T-branch structure having a short stub. One of the pair of the memory groups on the signal-reception side functions as an open end. Active termination is performed by a termination resistor of the other of the pair of the memory groups on the signal-non-reception side. Subsequently, signal reflections can be reduced.