Abstract: A semiconductor device having a chip-on-chip structure is constituted of a first semiconductor chip and even-numbered pairs of second semiconductor chips, all of which are laminated together on the surface of an interposer. The first semiconductor chip controls each pair of the second semiconductor chips so as to activate one second semiconductor chip while inactivating another second semiconductor chip. The second semiconductor chips are paired together in such a way that through-vias and electrodes thereof are positioned opposite to each other via bumps. Since drive voltage electrodes supplied with a drive voltage (VDD) and reference potential electrodes supplied with a reference potential (VSS) are mutually connected together between the paired second semiconductor chips, it is possible to increase the overall electrostatic capacitance of each second semiconductor chip so as to substantially reduce feed noise without increasing the overall layout area of the semiconductor device.

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.

Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

Abstract: As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

Abstract: In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.

Abstract: A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 ?m therebetween.

Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

Abstract: A memory module has a plurality of DRAMs (115), which share a bus line, on the front surface and the back surface of a board. The bus line is connected through a via hole (113) from a terminal (111) to one end of a strip line (112), and the other end of the strip line is connected to a strip line in the other layer through a via hole (119) provided for looping back the line. A termination resistor (120), provided near a termination voltage terminal (VTT), is connected to the looped-back strip line in the other layer through a via hole. The DRAM terminals are connected to the strip line each through a via hole. This memory module is mounted on a motherboard, on which a memory controller is provided, through a connector. The effective characteristic impedance of the bus line is matched with the characteristic impedance of the line in the motherboard.

Abstract: A COC DRAM including a plurality of stacked DRAM chips is mounted on a motherboard by using an interposer. The interposer includes a Si unit and a PCB. The Si unit includes a Si substrate and an insulating-layer unit in which wiring is installed. The PCB includes a reference plane for the wiring in the Si unit. The wiring topology between a chip set and the COC DRAM is the same for every signal. Accordingly, a memory system enabling a high-speed operation, low power consumption, and large capacity is provided.

Abstract: Input circuit ensuring a noise margin for a reference voltage. A semiconductor chip 11a comprises a pad 14 that inputs a reference voltage Vref, an input circuit 13, a resistance element R1 connected between an input terminal of the input circuit 13 and the pad 14, a capacitance element C1 connected between the input terminal of the input circuit 13 and a power supply VDD, and a capacitance element C2 connected between the input terminal of the input circuit 13 and a ground VSS within the semiconductor chip. A resistance value of the resistance element R1 is set based on an impedance characteristic of a network, for supplying the reference voltage Vref.

Abstract: In the simulation method of the present invention; one parameter is first selected from a plurality of parameters that relate to input/output characteristics. Next, regarding setting lines provided in a file for setting necessary choices from among a plurality of choices for a selected parameter, it is determined to either set choices by means of comment symbols that cause non-execution of the relevant lines, or set choices by means of identification codes, which are identifiers common to chips in which the same choice are to be set. When choices are to be set by means of comment symbols, the comment symbols of the setting lines of the necessary choices among the plurality of choices are deleted to make these setting lines effective. Alternatively, when choices are to be set by means of identification codes, the identification codes included in setting lines are rewritten to information for setting to the necessary choices. Finally, the simulation is executed.

Abstract: In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer.

Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

Abstract: A semiconductor device module includes a wiring substrate, a plurality of stacked semiconductor devices and a damping impedance circuit. The plurality of stacked semiconductor devices are provided on the wiring substrate and connected with a signal in a stubless manner, and each of the plurality of stacked semiconductor devices comprises a plurality of semiconductor chips which are stacked. The damping impedance circuit is provided for a transmission path of the signal for an uppermost semiconductor chip as the furthest one, from the wiring substrate, of the plurality of semiconductor chips of a first stacked semiconductor device as one of the plurality of stacked semiconductor devices which is first supplied with the signal.

Abstract: A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

Abstract: In a prior art, there has been a method in which a power supply line of an output buffer and that of a control circuit are independently provided so that the power supply noise occurring in the control circuit will not affect the output buffer. However, this method has had the problems that it increases both the number of power supply/grounding pins and power feed line inductance. The present invention provides a technique which, without causing the above two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer.

Abstract: Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit. A signal obtained by frequency-dividing a signal outputted from the variable delay circuit is supplied to one input of a phase comparator through a dummy delay circuit, and a signal obtained by frequency-dividing the input of the variable delay circuit is supplied to the other input of the phase comparator. Phase control is performed according to the result of comparison between the phases of both signals. Control on the speed of operation of a delay loop from the output of a variable delay circuit to a delay control input thereof is performed. For example, frequency-dividing circuits are respectively placed at the input and output of the variable delay circuit.