Abstract: A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.

Abstract: The semiconductor device includes an output driver and a characteristic switching circuit that switches characteristics of the output driver. The characteristic switching circuit mutually matches a rising time and a falling time of an output signal output from the output driver, when a power voltage supplied to a power line is a first voltage, with a rising time and a falling time of the output signal output from the output driver, when the power voltage supplied to the power line is a second voltage. As a result, an increase in an influence of a harmonic component or a crosstalk when the power voltage is reduced does not occur. Moreover, because a receiving condition on a receiver side does not change even when the power voltage is reduced, signal transmission and reception can be performed correctly irrespective of the power voltage.

Abstract: Regular chip packages that store user data therein and error-correction chip packages that store an error correction code therein are mounted on a module substrate. The module substrate has first and second mounting areas of different coordinates in an X direction, and the second mounting area has third and fourth mounting areas of different Y coordinates. The regular packages are oppositely arranged in the first mounting area on a surface and the back surface of the module substrate. The error-correction chip packages are oppositely arranged in the third mounting area on the surface and the back surface of the module substrate. A memory buffer that buffers user data and an error correction code is arranged in the fourth mounting area.

Abstract: A memory buffer mounted on a memory module includes a pre-launch function of advancing outputs of address/command signal and a post-launch function of delaying outputs of control signal. A time step increment for pre/post-launch time adjustment is set to be equal to or finer than tCK/32 where tCK is one clock cycle.

Abstract: A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter connected to the input terminal for passing a component of the reference voltage of the reference signal and eliminating undesired high frequency components, and one or more input first-stage circuits to each of which an output of the low-pass filter and a signal having the logic level to be determined are connected. In the memory device, the low-pass filter has predetermined attenuation at least at a frequency of an operating clock.

Abstract: In a signal transmission system, performing signal transmission via signal interconnections 4-1 to 4-3 between a memory 1 and a memory controller 2 mounted on a printed circuit board 3, noise or jitter may tend to be increased in the memory 1 and in the memory controller 2 at a specified data rate due to interconnection length resonance. Registers 6-1 and 6-2 are provided to hold information on the data rate. These registers 6-1 and 6-2 are provided in the signal transmission system along with a control system that modifies the relationship between clock frequency and interconnection length. The data rate or the propagation delay time is controlled to allow for avoiding the resonance.

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract: A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.

Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

Abstract: A semiconductor module includes a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device includes a first electrode. The second semiconductor device includes a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.

Abstract: A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

Abstract: A plurality of vias is disposed side by side on a multilayer board. A first via which is one of the vias disposed at one outer portion is electrically connected to a first outgoing line provided on the multilayer board. A second via at the other outer portion is electrically connected to a second outgoing line provided on the multilayer board. A plurality of the vias is connected to a first fixed potential layer (a ground layer, for example) of the multilayer board. At least one second fixed potential layer is provided, with a plurality of the vias through a clearance and having the same potential as that of the first fixed potential layer, as an inner layer of the multilayer board between the first and second outgoing lines and the fixed potential layer. Therefore, a BPF whose rate of occupied area is low is formed on the multilayer board without additional production processes.

Abstract: A method for designing a semiconductor package is disclosed, wherein the semiconductor package comprises a semiconductor chip and an adjustment target. A first target variable is calculated in consideration of a first transition state where an output level of the semiconductor chip changes from a low level to a high level. A second target variable is calculated in consideration of a second transition state where an output level of the semiconductor chip changes from the high level to the low level. Inferior one of the first and the second target variables is selected as a main target variable. The main target variable and a predetermined constraint represented in frequency domain are compared to decide design guidelines for the adjustment target.

Abstract: A method for designing a semiconductor apparatus comprising a semiconductor package in consideration of power integrity for a semiconductor chip included in the semiconductor package is disclosed. A target variable for an adjustment target is calculated on the basis of target information about the adjustment target, wherein the target variable is represented in frequency domain, and the adjustment target includes a part of the semiconductor package. The target variable is compared with a predetermined constraint, which is represented in frequency domain, to identify a problematic section, wherein the problematic section corresponds to a frequency region at which the target variable exceeds the predetermined constraint. Design guidelines are decided to solve the identified problematic section.

Abstract: A novel memory module with a multiple-rank configuration is provided to solve the problem that high-speed operation is impossible due to the fact that timing of a data strobe signal input to a memory is deviated from timing of a clock signal input thereto. In the memory module, a load capacity is provided at the vicinity of a clock signal input pin of a phase-locked loop circuit where the clock signal is input to match a time constant of a data strobe signal line with a time constant of a clock signal line. The matching of the input timings of the clock signal and the data strobe signal input to the memory enables the memory module to operate at a high speed.

Abstract: A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.

Abstract: A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.

Abstract: In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract: A semiconductor device is provided which includes: a first semiconductor integrated circuit; a ground line and a power supply line trough which electric power is supplied to the first semiconductor integrated circuit; and a variable impedance component which is connected between the ground line and the power supply line.