Abstract: A memory module of the unbuffered type with ECC function is employed. Configuration of an internal C/A bus is set to a single T-branch topology. An output impedance of a chipset is maintained substantially constant. A capacitor for cutting high-frequency components of a C/A signal is added on a C/A bus.

Abstract: A large difference in the lengths of the passages or a large difference in the load capacitances inclusive of parasitic elements of parallel data wirings can cause differences in the propagation time of data on the parallel data wirings. The invention provides a simultaneous arrival judging circuit for comparing phases of part or whole bits of data received from the parallel data wirings, and a timing adjusting mechanism for adjusting phases among parallel bits of the received data based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at a receiver.

Abstract: In a memory device having a controller and multiple memory modules both of which are mounted together on a motherboard, a high-speed operation is executed by suppressing waveform distortion caused by signal reflection. Since signal reflection occurs when a controller performs the writing/reading of data relative to memory units on memory modules, active terminator units are included in the controller and the memory units. These active terminator units are provided for a data bus and/or a clock bus in order to terminate these buses in memory units. The active terminator units provided for the controller and the memory units may be put into an inactive state when data is to be received.

Abstract: A memory module is provided with a resistor serving as an impedance adjuster which is connected directly or indirectly to an output terminal of an output transistor of a C/A register. The resistor adjusts the output impedance of the C/A register viewed from an input terminal of a C/A bus in such a manner that the output impedance becomes substantially constant within an operating voltage range of an internal signal output from the C/A register. The memory module is further provided with a capacitor serving as a rise time/fall time adjuster which adjusts rise time and fall time of the internal signal to specific values such that satisfactory waveforms are obtained.

Abstract: First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of 1/2 of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of singals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

Abstract: A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized.

Abstract: A maximum value of the number of mounted memory devices is assumed, and a value of an external delay replica is fixed and set. A desired frequency band is divided into a plurality of sub-frequency bands, and delay times of an output buffer and an internal delay replica are switched and used every sub-frequency band, thereby setting an actual maximum value and an actual minimum value to the internal delay replica. A selecting pin can select the delay time in the internal delay replica. Thus, it is possible to sufficiently ensure a set-up time and a hold time of an internal clock signal generated by a delay locked loop circuit in the latch operation in a register within a desired frequency band and with a permittable number of memory devices, irrespective of the frequency level and the number of mounted memory devices.

Abstract: A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized.

Abstract: The object of the present invention to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.

Abstract: A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

Abstract: A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each of the individual memory modules are connected in serial form, and each of the individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

Abstract: A process for producing a sealed container from a tubular blank of square cross section by folding and sealing a container bottom forming portion of the blank to form a flat bottom includes the step of sealing the bottom by collapsing an opening edge part of the container bottom forming portion to a flat form and sealing opposed walls of the collapsed opening edge part as lapped over each other to form a straight bottom seal rib.

Abstract: A container plug attaching device for attaching to an edge portion of a container defining an outlet O thereof a tubular plug P having an opening at one end and a flange F around an edge portion defining the opening comprises an anvil 33 and a sealing member 36 for clamping therebetween the container edge portion and the flange F as pressed against the container edge portion for sealing, a rotary shaft 31 having the anvil 33 mounted thereon and projecting radially thereof, a projection 61 provided on an outer end portion of a clamping face 32 of the anvil 33, drive means for intermittently rotating the rotary shaft 31 so as to stop the anvil 33 only in a sealing posture with the projection 61 opposed to the sealing member 36, and supply means for supplying the plug P to the anvil 33 in rotation for the projection 61 to hold the plug P as fitted thereover.

Abstract: A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each individual memory modules are connected in serial form, and each individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

Abstract: A memory system comprises a controller capable of controlling a memory operation, and memory connectors capable of mounting memory modules therein, both of which are provided on a system board. Each of the memory modules has a plurality of memory chips connected to module data wirings and module power wirings respectively. The module data wirings of each memory module are connected in series form through series paths lying within the connectors. Each individual module data wirings do not constitute branch wirings to system data wirings on the system board. Thus, such signal reflection as caused by branching from the data wirings on the system board is not developed. Since the power is supplied in parallel from the system board through parallel paths lying within the connectors, the supply of the power is stabilized.

Abstract: A filling nozzle cleaning device comprises an adaptor 74 having an upward socket 131 connectable to a downward discharge outlet 51 of a filling nozzle 41 disposed above a bed 11, a collecting pipe 73 having a vertical pipe portion 121 communicating with the socket 131 and extending through the bed 11 rotatably and upwardly and downwardly movably, and a drive mechanism for moving the adaptor 74 so as to advance the socket 131 to or retract the socket 131 from below the discharge outlet 51 and connect the socket 131 to the discharge outlet 51 when the socket is advanced. The drive mechanism has a rotary actuator 161 and a fluid pressure cylinder 165 which are connected to the vertical pipe portion 121 below the bed 11 for rotating and upwardly and downwardly moving the pipe portion 121.

Abstract: A packaging machine comprises a movable body having mandrels and intermittently drivable so as to stop each of the mandrels at a process station while carrying containers as fitted around the respective mandrels with a bottom forming portion of each container projecting outward from the mandrel, and a bottom breaker for forming folds in a bottom forming end portion of the container fitted around the mandrel as halted at the process station so as to render the end portion foldable flat. The bottom breaker has first folding means for initially folding the second and fourth bottom panels in two into triangles, and second folding means for subsequently folding first and third bottom panels. The second folding means has an upstream arm movable into pressing contact with the first bottom panel, and a downstream arm movable into pressing contact with the third bottom panel. The downstream arm is provided with a pressure plate at a portion thereof to be contacted with the third bottom panel.

Abstract: A filling nozzle cleaning device comprises an adaptor 74 having an upward socket 131 connectable to a downward discharge outlet 51 of a filling nozzle 41 disposed above a bed 11, a collecting pipe 73 having a vertical pipe portion 121 communicating with the socket 131 and extending through the bed 11 rotatably and upwardly and downwardly movably, and a drive mechanism for moving the adaptor 74 so as to advance the socket 131 to or retract the socket 131 from below the discharge outlet 51 and connect the socket 131 to the discharge outlet 51 when the socket is advanced. The drive mechanism has a rotary actuator 161 and a fluid pressure cylinder 165 which are connected to the vertical pipe portion 121 below the bed 11 for rotating and upwardly and downwardly moving the pipe portion 121.

Abstract: The invention provides a liquid metering and filling lifter for use with different kinds of containers C having different heights for moving the container C upward and downward with a stroke corresponding to the height of the container C in filling a liquid into the container, the lifter comprising a container pushing-up vertical lift rod 32 disposed below a filling nozzle 13 above a bed 11 and extending through the bed 11, the lift rod 32 having a container support 31 fixed to an upper end thereof, a container pushing-down vertical lift rod 34 extending through the bed 11 at one side of the lift rod 32 and having a container holder 33 fixed to an upper end thereof, and coupling means 35 disposed below the bed 11 for coupling the two lift rods 32, 34 to make the lift rods movable upward or downward together and uncoupling the lift rods 32, 34 to make the lift rods movable upward or downward individually.

Abstract: When there is a difference in the lengths of the passages among the parallel data wirings or a difference in the load capacitances inclusive of parasitic elements, a difference in the propagation time among the data becomes no longer negligible. At the time of transmitting data at high speeds in a short period, in particular, the setup time for receiving the data and the holding time are no longer maintained, and the data are not normally transmitted. In a data transmitter provided to address this problem, the receiver for receiving parallel data is provided with a simultaneous arrival judging circuit for comparing phases of part or whole bits of the received data, and with a timing adjusting mechanism for adjusting phases among the parallel bits at a point of receiving data in the receiver based on the judged results of the simultaneous arrival judging circuit, so that the data bits arrive simultaneously at the receiver.