Patents by Inventor Yong Chen

Yong Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6541309
    Abstract: A process of fabricating a molecular electronic device that preserves the integrity of the active molecular layer of the electronic device during processing is described. In one aspect, a barrier layer is provided to protect a molecular layer sandwiched between a bottom wire layer and a top wire layer from degradation during patterning of the top wire layer. A molecular electronic device structure and a memory system that are formed from this fabrication process are described.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: April 1, 2003
    Assignee: Hewlett-Packard Development Company LP
    Inventor: Yong Chen
  • Patent number: 6542400
    Abstract: A molecular memory system that includes a protective layer that is disposed over a molecular recording layer is described. The protective layer enables a scanning probe to write information to and read information from a molecular memory element by direct electrical contact without substantial risk of damage to either the scanning probe or the molecular recording medium. In this way, the invention avoids the high emission currents, which may damage the probe electrode or the recording media, or both, and avoids other difficulties often associated molecular memory systems with non-contacting probe electrodes.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: April 1, 2003
    Assignee: Hewlett-Packard Development Company LP
    Inventors: Yong Chen, Robert G. Walmsley
  • Patent number: 6518156
    Abstract: Configurable electronic circuits comprise arrays of cross-points of one layer of metal/semiconductive nanoscale lines crossed by a second layer of metal/semiconductive nanoscale lines, with a configurable layer between the lines. Methods are provided for altering the thickness and/or resistance of the configurable layer by oxidation or reduction methods, employing a solid material as the configurable layer. Specifically a method is provided for configuring nanoscale devices in a crossbar array of configurable devices comprising arrays of cross-points of a first layer of nanoscale lines comprising a first metal or a first semiconductor material crossed by a second layer of nanoscale lines comprising a second metal or a second semiconductor material.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: February 11, 2003
    Assignee: Hewlett-Packard Company
    Inventors: Yong Chen, R. Stanley Williams
  • Publication number: 20030008505
    Abstract: Self-assembled nanowires are provided, comprising nanowires of a first crystalline composition formed on a substrate of a second crystalline composition. The two crystalline materials are characterized by an asymmetric lattice mismatch, in which in the interfacial plane between the two materials, the first material has a close lattice match (in any direction) with the second material and has a large lattice mismatch in all other major crystallographic directions with the second material. This allows the unrestricted growth of the epitaxial crystal in the first direction, but limits the width in the other. The nanowires are grown by first selecting the appropriate combination of materials that fulfill the foregoing criteria. The surface of the substrate on which the nanowires are to be formed must be cleaned in order (1) to ensure that the surface has an atomically flat, regular atomic structure on terraces and regular steps and (2) to remove impurities.
    Type: Application
    Filed: November 13, 2001
    Publication date: January 9, 2003
    Inventors: Yong Chen, R. Stanley Williams, Douglas A. A. Ohlberg
  • Publication number: 20030003775
    Abstract: A method of fabricating a molecular electronic device or crossbar memory device is provided. The device comprises at least one pair of crossed wires and a molecular switch film therebetween. The method comprises: (a) forming at least one bottom electrode on a substrate by first forming a first layer on the substrate and patterning the first layer to form the bottom electrode by an imprinting technique; (b) forming the molecular switch film on top of the bottom electrode; (c) optionally forming a protective layer on top of the molecular switch film to avoid damage thereto during further processing; (d) coating a polymer layer on top of the protective layer and patterned the polymer layer by the imprinting method to form openings that expose portions of the protective layer; and (e) forming at least one top electrode on the protective layer through the openings in the polymer layer by first forming a second layer on the polymer layer and patterning the second layer.
    Type: Application
    Filed: September 26, 2001
    Publication date: January 2, 2003
    Inventor: Yong Chen
  • Patent number: 6500257
    Abstract: An epitaxial material grown laterally in a trench allows for the fabrication of a trench-based semiconductor material that is substantially low in dislocation density. Initiating the growth from a sidewall of a trench minimizes the density of dislocations present in the lattice growth template, which minimizes the dislocation density in the regrown material. Also, by allowing the regrowth to fill and overflow the trench, the low dislocation density material can cover the entire surface of the substrate upon which the low dislocation density material is grown. Furthermore, with successive iterations of the trench growth procedure, higher quality material can be obtained. Devices that require a stable, high quality epitaxial material can then be fabricated from the low dislocation density material.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: December 31, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Shih-Yuan Wang, Changhua Chen, Yong Chen, Scott W. Corzine, R. Scott Kern, Richard P. Schneider, Jr.
  • Patent number: 6498168
    Abstract: Di-N-substituted piperazine or 1,4 di-substituted piperadine compounds in accordance with formula I (including all isomers, salts, esters, and solvates) wherein R, R1, R2, R3, R4, R21, R27, R28, X, Y, and Z are as defined herein are muscarinic antagonists useful for treating cognitive disorders such as Alzheimer's disease. Pharmaceutical compositions and methods of preparation are also disclosed. Also disclosed are synergistic combinations of compounds of the above formula or other compounds capable of enhancing acetylcholine release with acetylcholinesterase inhibitors.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: December 24, 2002
    Assignee: Schering Corporation
    Inventors: Derek Lowe, Wei Chang, Joseph Kozlowski, Joel G. Berger, Robert McQuade, Allen Barnett, Margaret Sherlock, Wing Tom, Sundeep Dugar, Lian-Yong Chen, John W Clader, Samuel Chackalamannil, Wang Yuguang, Stuart W. McCombie, Jayaram R. Tagat, Susan F. Vice, Wayne Vaccaro, Michael J. Green, Margaret E. Browne, Theodros Asberom
  • Publication number: 20020172064
    Abstract: A process of fabricating a molecular electronic device that preserves the integrity of the active molecular layer of the electronic device during processing is described. In one aspect, a passivation layer is provided to protect a molecular layer from degradation during patterning of the top wire layer. A molecular electronic device structure and a memory system that are formed from this fabrication process are described.
    Type: Application
    Filed: March 22, 2001
    Publication date: November 21, 2002
    Inventor: Yong Chen
  • Publication number: 20020171148
    Abstract: A process of fabricating a molecular electronic device that preserves the integrity of the active molecular layer of the electronic device during processing is described. In one aspect, a barrier layer is provided to protect a molecular layer sandwiched between a bottom wire layer and a top wire layer from degradation during patterning of the top wire layer. A molecular electronic device structure and a memory system that are formed from this fabrication process are described.
    Type: Application
    Filed: March 21, 2001
    Publication date: November 21, 2002
    Inventor: Yong Chen
  • Publication number: 20020170880
    Abstract: The lithographic process described herein involves aligning a patterned mold with respect to an alignment mark that is disposed on a substrate based upon interaction of a scanning probe with the alignment mark. By this method, the patterned mold may be aligned to an atomic accuracy (e.g., on the order of 10 nm or less), enabling nanometer-scale devices to be fabricated. A device formed by this lithographic method and a system for implementing this lithographic method with alignment also are described.
    Type: Application
    Filed: March 22, 2001
    Publication date: November 21, 2002
    Inventor: Yong Chen
  • Publication number: 20020172072
    Abstract: A molecular memory system that includes a protective layer that is disposed over a molecular recording layer is described. The protective layer enables a scanning probe to write information to and read information from a molecular memory element by direct electrical contact without substantial risk of damage to either the scanning probe or the molecular recording medium. In this way, the invention avoids the high emission currents, which may damage the probe electrode or the recording media, or both, and avoids other difficulties often associated molecular memory systems with non-contacting probe electrodes.
    Type: Application
    Filed: March 27, 2001
    Publication date: November 21, 2002
    Inventors: Yong Chen, Robert G. Walmsley
  • Patent number: 6432740
    Abstract: A method of fabricating a molecular electronic device or crossbar memory device is provided. The device comprises at least one pair of crossed wires and a molecular switch film therebetween. The method comprises: (a) forming at least one bottom electrode on a substrate by first forming a first layer on the substrate and patterning the first layer to form the bottom electrode by an imprinting technique; (b) forming the molecular switch film on top of the bottom electrode; (c) optionally forming a protective layer on top of the molecular switch film to avoid damage thereto during further processing; (d) coating a polymer layer on top of the protective layer and patterned the polymer layer by the imprinting method to form openings that expose portions of the protective layer; and (e) forming at least one top electrode on the protective layer through the openings in the polymer layer by first forming a second layer on the polymer layer and patterning the second layer.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: August 13, 2002
    Assignee: Hewlett-Packard Company
    Inventor: Yong Chen
  • Patent number: 6429466
    Abstract: A method for growing a crystalline layer that includes a first material on a growth surface of a crystalline substrate of a second material, wherein the first material and the second material have different lattice constants. A buried layer is generated in the substrate such that the buried layer isolates a layer of the substrate that includes the growth surface from the remainder of the substrate. The second material is then deposited on the growth surface at a growth temperature. The isolated layer of the substrate has a thickness that is less than the thickness at which defects are caused in the crystalline lattice of the first material by the second material crystallizing thereon. The buried layer is sufficiently malleable at the growth temperature to allow the deformation of the lattice of the isolated layer without deforming the remainder of the substrate. The present invention may be utilized for growing III-V semiconducting material layers on silicon substrates.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: August 6, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Yong Chen, Scott W. Corzine, Theodore I. Kamins, Michael J. Ludowise, Pierre H. Mertz, Shih-Yuan Wang
  • Publication number: 20020103205
    Abstract: Di-N-substituted piperazine or 1,4 di-substituted piperadine compounds in accordance with formula I (including all isomers, salts, esters, and solvates) 1
    Type: Application
    Filed: July 11, 2001
    Publication date: August 1, 2002
    Inventors: Derek Lowe, Wei Chang, Joseph Kozlowski, Joel G. Berger, Robert McQuade, Allen Barnett, Margaret Sherlock, Wing Tom, Sundeep Dugar, Lian-Yong Chen, John W. Clader, Samuel Chackalamannil, Wang Yuguang, Stuart W. McCombie, Jayaram R. Tagat, Susan F. Vice, Wayne Vaccaro, Michael J. Green, Margaret E. Browne, Theodros Asberom
  • Publication number: 20020075420
    Abstract: An electric field activated molecular system, preferably bi-stable, configured within an electric field generated by a pair of electrodes is provided for use, e.g., as electronic ink or other visual displays. The molecular system has an electric field induced band gap change that occurs via a change (reversible or irreversible) of the extent of the electron conjugation via chemical bonding change to change the band gap, wherein in a first state, there is substantial conjugation throughout the molecular system, resulting in a relatively smaller band gap, and wherein in a second state, the substantial conjugation is destroyed, resulting in a relatively larger band gap. The changing of substantial conjugation may be accomplished in one of the following ways: (1) charge separation or recombination accompanied by increasing or decreasing electron localization in the molecule; or (2) change of substantial conjugation via charge separation or recombination and &pgr;-bond breaking or making.
    Type: Application
    Filed: August 17, 2001
    Publication date: June 20, 2002
    Inventors: Xiao-An Zhang, Alexandre Bratkovski, Yong Chen, R. Stanley Williams, Kent D. Vincent
  • Publication number: 20020075925
    Abstract: A laser diode that is constructed in a trench in a manner such that the material in the trench acts as a waveguide. The laser diode includes a first contact layer constructed from a first semiconducting material of a first carrier type, the first semiconducting material having a first index of refraction. The first contact layer has a trench therein. The trench has a layer of a second semiconducting material of the first carrier type on the bottom surface. The index of refraction of the second semiconducting material is at least one percent greater than the index of refraction of the first semiconducting material. The laser also includes a first dielectric layer covering the first layer in those regions outside of the trench and a first cladding layer constructed from a third semiconducting material of the first carrier type. The first cladding layer overlies the dielectric layer. An active layer overlies the first cladding layer.
    Type: Application
    Filed: October 26, 2001
    Publication date: June 20, 2002
    Inventors: Shih-Yuan Wang, Yong Chen
  • Patent number: 6407443
    Abstract: A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate; (c) cleaving the stack normal to its major surface to expose the plurality of alternating layers; and (d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology. The pattern of the platen is then imprinted into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing to form nanowires.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: June 18, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Yong Chen, R. Stanley Williams
  • Patent number: 6376269
    Abstract: A current confinement region located proximate to a pair of Bragg reflectors in a semiconductor laser and an epitaxial lateral overgrowth layer grown through an aperture in the current confinement region allows a desirable current flow in the laser. The placement of the current confinement region having an aperture formed therein allows the desired current flow through an active layer of the laser. This current flow allows the laser to achieve a single spatial mode output. Furthermore, the ability to place a pair of Bragg reflectors in close proximity to each other achieves a short optical cavity resulting in a single longitudinal mode output. Together, the single spatial mode and single longitudinal mode result in a desired single frequency output. The single frequency output is particularly useful for high speed, high rate optical and telecommunications.
    Type: Grant
    Filed: February 2, 1999
    Date of Patent: April 23, 2002
    Assignee: Agilent Technologies, Inc.
    Inventors: Yong Chen, Shin-Yuan Wang
  • Patent number: 6327288
    Abstract: A laser diode that is constructed in a trench in a manner such that the material in the trench acts as a waveguide. The laser diode includes a first contact layer constructed from a first semiconducting material of a first carrier type, the first semiconducting material having a first index of refraction. The first contact layer has a trench therein. The trench has a layer of a second semiconducting material of the first carrier type on the bottom surface. The index of refraction of the second semiconducting material is at least one percent greater than the index of refraction of the first semiconducting material. The laser also includes a first dielectric layer covering the first layer in those regions outside of the trench and a first cladding layer constructed from a third semiconducting material of the first carrier type. The first cladding layer overlies the dielectric layer. An active layer overlies the first cladding layer.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: December 4, 2001
    Assignee: LumiLeds Lighting, U.S., LLC
    Inventors: Shih-Yuan Wang, Yong Chen
  • Publication number: 20010044200
    Abstract: A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate; (c) cleaving the stack normal to its major surface to expose the plurality of alternating layers; and (d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology. The pattern of the platen is then imprinted into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing to form nanowires.
    Type: Application
    Filed: June 20, 2001
    Publication date: November 22, 2001
    Inventors: Yong Chen, R. Stanley Williams