Abstract: Disclosed is a shift register capable of preventing charges supplied to a Q node to turn on a pull-up transistor for outputting a scan pulse from leaking outwards. The shift register includes a plurality of stages connected to gate lines formed at a panel. Each stage includes a scan signal generator for generating a scan pulse or a turn-off signal, a scan pulse controller for generating a Q-node control signal for generation of the scan pulse, a Q-node adjuster for preventing the Q-node control signal from leaking outwards during supply of the Q-node control signal to a Q-node connected to the scan signal generator, and a turn-off signal controller for transferring a Qb-node control signal for generation of the turn-off signal to the scan signal generator via a Qb-node when no scan pulse is generated from the scan signal generator.

Abstract: A shift register includes a plurality of stages each outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node. The voltage at the at least one A-reset node and any one A-clock pulse, at least one B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.

Abstract: Disclosed is a shift register capable of stably generating an output even when the threadhold voltage of a pull-down switching element is raised due to degradation of the pull-down switching element. The shift register includes a plurality of stages each comprising a node controller comprising an inverter to control a voltage at a reset node in accordance with a voltage at a set node, and an output unit to output a scan pulse based on at least one of the voltage at the set node and the voltage at the reset node. The shift register further includes an inverter voltage controller for controlling a high-level inverter voltage supplied to each inverter of the stages based on the voltage at at least one reset node in at least one of the stages.

Abstract: A shift register capable of preventing leakage current and a display device using the same are disclosed. The shift register includes a plurality of stages. Each stage includes a set unit setting a Q node in response to a start pulse or previous output, an inverter for controlling a QB node to have a logic state opposite to that of the Q node, an output unit for outputting any one input clock or a gate off voltage in response to the logic states of the Q and QB nodes, a reset unit including a reset switching element, the reset switching element resetting the Q node with a first reset voltage in response to a reset pulse or next output, and a noise cleaner resetting the Q node with a second reset voltage in response to the QB node. When the reset switching element is turned off, the first reset voltage is greater than a voltage of the reset pulse or the next output for the current.

Abstract: A shift register includes a plurality of stages each for outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes k A-sub-stages each for controlling a voltage at an A-set node and a voltage at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse, a B-sub-stage for controlling a voltage at a B-set node and a voltage at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A display device includes a substrate with a display area having gate lines and data lines defining cells that each has a pixel electrode, a driving circuit on the substrate, at least one first signal line including lower and upper lines overlapping each other with an insulation layer interposed therebetween, the first signal line adjacent to the driving circuit, and at least one second signal line to connect the first signal line to the driving circuit.

Abstract: A built-in gate driver includes a shift register provided in a non-display area of a panel, and configured to include first to gth stages outputting a scan signal, a clock supply line part configured to include m number of clock supply lines connected to the shift register, and a power supply line part configured to include n number of power supply lines connected to the shift register. At least one of the lines of the clock supply lines and the power supply lines are in a first side direction of the shift register, and the other at least one or more lines of the clock supply lines and the power supply lines are in a second side direction of the shift register.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.

Abstract: Disclosed is a shift register capable of stably generating an output even when the threadhold voltage of a pull-down switching element is raised due to degradation of the pull-down switching element. The shift register includes a plurality of stages each comprising a node controller comprising an inverter to control a voltage at a reset node in accordance with a voltage at a set node, and an output unit to output a scan pulse based on at least one of the voltage at the set node and the voltage at the reset node. The shift register further includes an inverter voltage controller for controlling a high-level inverter voltage supplied to each inverter of the stages based on the voltage at at least one reset node in at least one of the stages.

Abstract: A shift register is provided in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes stages for sequentially outputting scan pulses. An nth one of the stages includes a node controller for controlling voltages at nodes, and an output unit for outputting any one of a corresponding one of the scan pulses and a first discharging voltage according to the voltages at the nodes. The nodes include set and reset nodes. The node controller of the nth stage includes a first switching device controlled by a voltage supplied to the reset node for supplying a second discharging voltage to the set node, and an inverter circuit controlled by a voltage supplied to the set node for supplying any one of a charging voltage and a third discharging voltage to the reset node.

Abstract: A shift register includes a plurality of first to n-numbered stages, where n is a positive integer. Each stage includes a node controller controlling respective voltages of a first node and a second node in accordance with an output signal from the (i?j1)-numbered stage and an output signal from the (i+j2)-numbered stage, wherein i is a positive integer from 1 to n, j1 is a positive integer greater than or equal to 2, and j2 is a positive integer equal to or different from j1; and an output unit outputting one of a plurality of clock signals in accordance with the respective voltages of the first and second nodes.

Abstract: Disclosed herein is a shift register which is capable of preventing leakage of charges at a set node which occurs when the duty ratio of a scan pulse is small, so as to normally output a scan pulse. The shift register includes a plurality of stages for sequentially generating outputs thereof. Each of the stages includes a carry output unit for outputting a carry pulse to drive at least one of a downstream stage and an upstream stage, and a scan output unit for outputting a scan pulse to drive a gate line. Each of the outputs generated from the stages includes the carry pulse and the scan pulse. The carry pulse and the scan pulse are paired to correspond to each other. The paired carry pulse and scan pulse have different durations.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A shift register includes a plurality of stages each outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node. The voltage at the at least one A-reset node and any one A-clock pulse, at least one B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.

Abstract: A shift register includes a plurality of stages for sequentially outputting A-scan pulses and B-scan pulses. At least one of the stages includes an A-sub-stage for controlling a voltage at an A-set node and a voltage at at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the A-reset node and any one A-clock pulse, a B-sub-stage for controlling a voltage at a B-set node and a voltage at at least one B-reset node in response to an external B-control signal and generating a B-carry pulse based on the voltage at the B-set node, the voltage at the B-reset node and any one B1-clock pulse, and a scan output controller for generating a corresponding one of the A-scan pulses and a corresponding one of the B-scan pulses.

Abstract: A shift register includes a plurality of stages each for outputting k composite pulses each including an A-scan pulse and a B-scan pulse. At least one stage includes k A-sub-stages each for controlling a voltage at an A-set node and a voltage at least one A-reset node in response to an external A-control signal and generating an A-carry pulse based on the voltage at the A-set node, the voltage at the at least one A-reset node and any one A-clock pulse, a B-sub-stage for controlling a voltage at a B-set node and a voltage at least one B-reset node in response to an external B-control signal and generating a B-carry pulse, and a scan output controller for generating k A-scan pulses and k B-scan pulses and outputting one of the A-scan pulses and one of the B-scan pulses corresponding to each other as one composite pulse.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A shift register includes a plurality of stages, each of which outputs a carry pulse and a scan pulse. An nth one of the stages includes a carry output switching device controlled by a voltage applied to a set node and connected between a carry clock transfer line transferring any one of i carry clock pulses and a carry output terminal of the nth stage, a scan output switching device controlled by the voltage applied to the set node and connected between a scan clock transfer line transferring any one of j scan clock pulses and a scan output terminal of the nth stage, and a stabilization switching device controlled by any one of the i carry clock pulses and connected between a carry output terminal of an (n?p)th one of the stages and the set node or between a start transfer line and the set node.