Abstract: A shift register which is capable of minimizing a spike voltage is disclosed. The shift register includes a plurality of stages, each including a plurality of nodes, a scan pulse output unit controlled according to voltages at the nodes for outputting a scan pulse and supplying it to a corresponding gate line through a scan output terminal, a carry pulse output unit controlled according to the voltages at the nodes for outputting a carry pulse and supplying it to an upstream stage and a downstream stage through a carry output terminal, a node controller for controlling voltage states of the nodes in response to a carry pulse from the upstream stage and a carry pulse from the downstream stage, and a discharging unit connected to any one of a plurality of clock transfer lines and the scan output terminal for discharging a spike voltage of the scan output terminal.

Abstract: A shift register is disclosed, which can prevent a multi-output caused by a coupling phenomenon, the shift register comprising at least two clock transmission lines which transmit at least two clock pulses provided with the phase difference; and a plurality of stages which are supplied with the clock pulses from the clock transmission lines, and output output-signals in sequence, wherein each of the stages comprises a pull-up switching unit which is supplied with the first clock pulse, and outputs the first clock pulse as the output-signal according to a signal state of an enable node; and a noise eliminating unit which responds to the second clock pulse of which phase is prior to that of the first clock pulse supplied to the pull-up switching unit, and supplies a start pulse externally provided or the output-signal provided from the preceding stage to the enable node.

Abstract: A liquid crystal display (LCD) device includes an LCD panel having a plurality of data lines and a plurality of gate lines crossing the data lines, a data driving circuit to generate a data voltage, a demultiplexer to apply the data voltage from the data driving circuit to the data lines using a plurality of switching devices, and a control signal generator to generate a plurality of control signals having a first polarity of voltage in order to turn on the switching devices and in order to add a second polarity of voltage to the control signals.

Abstract: A liquid crystal display device includes a driving circuit provided with a switching device on a liquid crystal display panel, the switching device including a plurality of thin film transistors connected in parallel and commonly interconnected using a gate electrode.

Abstract: A driving circuit built in liquid crystal display panel for increasing an area of a driving circuit by an overlap between the driving circuit and a sealant is disclosed. In the driving circuit built in the liquid crystal display panel, a liquid crystal cell matrix is provided in a display area of first and second substrates joined to each other by a sealant. A driving circuit is provided in a circuit area of a non-display area of the display panel at an outer portion of the display area to drive the liquid crystal cell matrix. A plurality of LOG-type signal lines are provided at a LOG area of the non-display area to supply a plurality of signals required for the driving circuit. The driving circuit area and the LOG area overlaps with the sealant.

Abstract: In a gate driver including a plurality of stages sequentially outputting shifted signals, each of the stages includes a first controller for controlling a first node in response to a first scan signal and a second scan signal; a second controller for controlling second and third nodes in response to the first scan signal and a voltage at the first node; and an output unit for selectively outputting one of a plurality of clock signals and a first power supply voltage in response to voltages at the first, second and third nodes, wherein second and third power supply voltages different from each other are switched to be supplied to the second and third nodes.

Abstract: A shift register includes a plurality of stages for sequentially outputting scan pulses to drive a plurality of gate lines, wherein each of the stages includes a set node, a pull-up switching device for outputting a corresponding scan pulse according to a logic state of the set node, at least two reset nodes, at least two pull-down switching devices, each of the pull-down switching devices being connected to a corresponding reset node to output an off voltage according to a voltage level of the corresponding reset node, and a node controller for controlling logic states of the nodes of a corresponding stage and logic states of the nodes of stages different from the corresponding stage together, wherein the node controllers of the stages control an output order of the scan pulses from the stages according to a forward voltage and reverse voltage having opposite phases.

Abstract: A liquid crystal display device includes a driving circuit provided with a switching device on a liquid crystal display panel, the switching device including a plurality of thin film transistors connected in parallel and commonly interconnected using a gate electrode.

Abstract: A liquid crystal display device and a driving method thereof is presented in which a first liquid crystal cell is provided at one side of the data line, and a second liquid crystal cell is provided at the other side thereof. A first switching part is provided for each first liquid crystal cell positioned at an ith horizontal line (wherein i is an integer) to be controlled by the (i?1)th gate line and the ith gate line. A second switching part is provided for each second liquid crystal cell positioned at an ith horizontal line to be controlled by the ith gate line.

Abstract: A liquid crystal display device includes a driving circuit provided with a switching device on a liquid crystal display panel, the switching device including a plurality of thin film transistors connected in parallel and commonly interconnected using a gate electrode.

Abstract: A liquid crystal display device and a driving method thereof is presented in which a first liquid crystal cell is provided at one side of the data line, and a second liquid crystal cell is provided at the other side thereof. A first switching part is provided for each first liquid crystal cell positioned at an ith horizontal line (wherein i is an integer) to be controlled by the (i?1)th gate line and the ith gate line. A second switching part is provided for each second liquid crystal cell positioned at an ith horizontal line to be controlled by the ith gate line.

Abstract: A driving circuit for a flat panel display device includes shift register stages, each containing: a first TFT charging a Q node according to a start signal; a second TFT discharging the Q node according to an output voltage of a next shift register stage; a pull-up unit increasing an output voltage according to the Q node voltage; an odd pull-down unit decreasing the output voltage in an odd frame according to a QB-o node voltage; and an even pull-down unit decreasing the output voltage in an even frame according to a QB-e node voltage. A gate and drain of a third odd TFT connected to the QB-o node are connected to each other and receive an odd source voltage. A gate and drain of the third even TFT connected to the QB-e node are connected to each other and receive an even source voltage.

Abstract: A shift register includes first and second stages for sequentially outputting scan pulses to drive first and second gate lines. One of the first and second stages includes a pull-up switching device connected to an enabling node of the one of the first and second stages; a first pull-down switching device connected to a first disabling node of the one of the first and second stages; a second pull-down switching device connected to a second disabling node of the one of the first and second stages; and a node controller. The node controller of the first stage controls the logic state of each of the enabling node of the first stage, the first disabling node of the first stage and the first disabling node of the second stage. The node controller of the second stage controls the logic state of each of the enabling node of the second stage, the second disabling node of the second stage and the second disabling node of the first stage.

Abstract: A shift register includes a plurality of stages which output an output signal through an output signal line by using any three of a first voltage supply source, a previous stage's output signal, a next stage's output signal, and first to fourth clock signals. A pull-up transistor outputs the first clock signal through the output signal and a pull-down transistor supplies a supply voltage from the first voltage supply source to the output signal line. A Q node controller controls the logic value of the Q node in response to any one of the previous stage's output signal and the next stage's output signal. A Qb node controller controls the logic value of the Qb node.

Abstract: A built-in gate driver having an improved reliability and a display device having the same are provided. A transistor controlled by an output signal of a next stage is further provided and thus a node (Q) is rapidly discharged. Accordingly, the multi-output signals due to the reduced discharge of the node (Q) caused by the degradation of the transistor controlled by a node QB can be prevented. By including only one transistor for controlling the charge of the start pulse signal on the node (Q), it is possible to prevent a malfunction from occurring when the transistor connected to the clock is degraded by the periodic clock of a high state. Also, an image quality and the reliability of the gate driver can be improved.

Abstract: A liquid crystal display device and a driving method thereof for improving a picture quality are disclosed. In the liquid crystal display device, a plurality of liquid crystal cells is provided at crossings of a plurality of data lines and a plurality of gate lines. A first switching device supplies a voltage from the data line to the liquid crystal cell in response to a voltage at a control terminal. A second switching device applies a gate signal at the ith gate line (wherein i is an integer) to the control terminal in response to a voltage at the (i?1)th gate line, thereby charging said voltage of the control terminal.

Abstract: A gate driving apparatus for a liquid crystal display includes a shift register which is provided with first and second half-period clock signals having phases inverted with respect to each other and each having a pulse width of a half-period, first to fourth one-period clock signals having phases shifted sequentially and each having a pulse width of one period, a start pulse, a high-level supply voltage and a low-level supply voltage. The shift register generates a half-period output in response to the start pulse and the first and second half-period clock signals. The shift register also generates a one-period output at a half-period delay from an end time of the half-period output in response to any one of the first to fourth one-period clock signals.

Abstract: A driving circuit for a flat panel display device includes first and second generation units generating m-phase circulation enable control clocks and n-phase circulation form generation clocks; and a plurality of shift register stages generating output signals by using the m-phase circulation enable control clocks and the n-phase circulation form generation clocks. Each shift register stage includes an input terminal receiving the m-phase circulation enable control clocks; first and second nodes outputting first and second signals, respectively, using the m-phase circulation enable control clocks; a first transistor connected to the first node and receiving the n-phase circulation form generation clocks; a second transistor connected to the second node and the first transistor; and an output terminal between the first and second transistors and outputting one of the output signals.

Abstract: Disclosed herein is a liquid crystal display device which is capable of reducing the number of data drive integrated circuits (ICs) to curtail a production cost. The liquid crystal display device includes a plurality of pixel cells formed respectively in areas defined by a plurality of gate lines and a plurality of data lines, a first unit pixel including at least three of the pixel cells, the at least three pixel cells being connected to different ones of the data lines, and a second unit pixel including at least three of the pixel cells other than the at least three pixel cells of the first unit pixel, the at least three pixel cells of the second unit pixel being connected respectively to the different data lines to which the at least three pixel cells of the first unit pixel are connected, wherein the first and second unit pixels are arranged in a direction of the data lines and connected to different ones of the gate lines.

Abstract: An active matrix type display device is disclosed, to reduce a fabrication cost, which comprises first to third gate lines arranged at one direction; first and second data lines arranged orthogonally to the first to third gate lines; a first pixel cell connected to the first gate line and the first data line; a second pixel cell connected to the first gate line and the second data line; a third pixel cell connected to the second gate line and the first data line; a fourth pixel cell connected to the second gate line and the second data line; a fifth pixel cell connected to the third gate line and the first data line; and a sixth pixel cell connected to the third gate line and the second data line, wherein the three predetermined pixel cells of displaying the different colors among the first to sixth pixel cells constitute a first unit pixel for displaying a first unit image; and the three other pixel cells except the pixel cells included in the first unit pixel constitute a second unit pixel for displaying a