Abstract: A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.

Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.

Abstract: An active matrix type display device is disclosed, to reduce a fabrication cost, which comprises first to third gate lines arranged at one direction; first and second data lines arranged orthogonally to the first to third gate lines; a first pixel cell connected to the first gate line and the first data line; a second pixel cell connected to the first gate line and the second data line; a third pixel cell connected to the second gate line and the first data line; a fourth pixel cell connected to the second gate line and the second data line; a fifth pixel cell connected to the third gate line and the first data line; and a sixth pixel cell connected to the third gate line and the second data line, wherein the three predetermined pixel cells of displaying the different colors among the first to sixth pixel cells constitute a first unit pixel for displaying a first unit image; and the three other pixel cells except the pixel cells included in the first unit pixel constitute a second unit pixel for displaying a

Abstract: An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a-Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.

Abstract: A display apparatus is disclosed. The display apparatus includes: a plurality of scan signal lines and a plurality of data signal lines that cross each other; a plurality of pixels formed at each crossing of the scan signal lines and the data signal lines, wherein each of the pixels includes sub-pixels that display red color, green color, blue color and white color in response to a scan signal from the scan signal lines and a data signal from the data signal lines, wherein the sub-pixels are arranged in a 2×2 matrix; a scan signal driving circuit including a plurality of stages that supplies the scan signal to the scan signal lines; and a data signal driving circuit that supplies the data signal to the data signal lines, wherein the scan signal driving circuit, the pixels, the scan signal lines and the data signal lines are formed on a same substrate.

Abstract: An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a—Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.

Abstract: A display apparatus is disclosed. The display apparatus includes: a plurality of scan signal lines and a plurality of data signal lines that cross each other; a plurality of pixels formed at each crossing of the scan signal lines and the data signal lines, wherein each of the pixels includes a sub-pixels that display red color, green color, blue color and white color in response to a scan signal from the scan signal lines and a data signal from the data signal lines, wherein the sub-pixels are arranged in a 2×2 matrix; a scan signal driving circuit including a plurality of stages that supplies the scan signal to the scan signal lines; and a data signal driving circuit that supplies the data signal to the data signal lines, wherein the scan signal driving circuit, the pixels, the scan signal lines and the data signal lines are formed on a same substrate.

Abstract: A driving circuit of a display device and a method for driving the display device are disclosed which are capable of reducing distortion of scan pulses supplied to gate lines of a liquid crystal panel. The driving circuit includes a first shift register for sequentially supplying first scan pulses to one-side ends of gate lines included in a display, respectively, to sequentially drive the gate lines, the first shift register simultaneously driving at least two adjacent ones of the gate lines for a predetermined period of time, and a second shift register for sequentially supplying second scan pulses to the other-side ends of the gate lines, respectively, to sequentially drive the gate lines, the second shift register simultaneously driving at least two adjacent ones of the gate lines for a predetermined period of time.

Abstract: A gate driver includes a plurality of stage groups, a gate driving circuit, and an output controller. The gate driving circuit supplies the plurality of stage groups with a plurality of clock pulses. The plurality of stage groups supply the input clock pulses to associated gate lines of a liquid crystal panel. The output controller generates a plurality of control voltage signals that control which of the plurality of stage groups generate an output signal.

Abstract: A shift register which is capable of minimizing a spike voltage is disclosed. The shift register includes a plurality of stages, each including a plurality of nodes, a scan pulse output unit controlled according to voltages at the nodes for outputting a scan pulse and supplying it to a corresponding gate line through a scan output terminal, a carry pulse output unit controlled according to the voltages at the nodes for outputting a carry pulse and supplying it to an upstream stage and a downstream stage through a carry output terminal, a node controller for controlling voltage states of the nodes in response to a carry pulse from the upstream stage and a carry pulse from the downstream stage, and a discharging unit connected to any one of a plurality of clock transfer lines and the scan output terminal for discharging a spike voltage of the scan output terminal.

Abstract: A shift register is disclosed, which can prevent a multi-output caused by a coupling phenomenon, the shift register comprising at least two clock transmission lines which transmit at least two clock pulses provided with the phase difference; and a plurality of stages which are supplied with the clock pulses from the clock transmission lines, and output output-signals in sequence, wherein each of the stages comprises a pull-up switching unit which is supplied with the first clock pulse, and outputs the first clock pulse as the output-signal according to a signal state of an enable node; and a noise eliminating unit which responds to the second clock pulse of which phase is prior to that of the first clock pulse supplied to the pull-up switching unit, and supplies a start pulse externally provided or the output-signal provided from the preceding stage to the enable node.

Abstract: A liquid crystal display (LCD) device includes an LCD panel having a plurality of data lines and a plurality of gate lines crossing the data lines, a data driving circuit to generate a data voltage, a demultiplexer to apply the data voltage from the data driving circuit to the data lines using a plurality of switching devices, and a control signal generator to generate a plurality of control signals having a first polarity of voltage in order to turn on the switching devices and in order to add a second polarity of voltage to the control signals.

Abstract: A liquid crystal display device includes a driving circuit provided with a switching device on a liquid crystal display panel, the switching device including a plurality of thin film transistors connected in parallel and commonly interconnected using a gate electrode.

Abstract: A driving circuit built in liquid crystal display panel for increasing an area of a driving circuit by an overlap between the driving circuit and a sealant is disclosed. In the driving circuit built in the liquid crystal display panel, a liquid crystal cell matrix is provided in a display area of first and second substrates joined to each other by a sealant. A driving circuit is provided in a circuit area of a non-display area of the display panel at an outer portion of the display area to drive the liquid crystal cell matrix. A plurality of LOG-type signal lines are provided at a LOG area of the non-display area to supply a plurality of signals required for the driving circuit. The driving circuit area and the LOG area overlaps with the sealant.

Abstract: In a gate driver including a plurality of stages sequentially outputting shifted signals, each of the stages includes a first controller for controlling a first node in response to a first scan signal and a second scan signal; a second controller for controlling second and third nodes in response to the first scan signal and a voltage at the first node; and an output unit for selectively outputting one of a plurality of clock signals and a first power supply voltage in response to voltages at the first, second and third nodes, wherein second and third power supply voltages different from each other are switched to be supplied to the second and third nodes.

Abstract: A shift register includes a plurality of stages for sequentially outputting scan pulses to drive a plurality of gate lines, wherein each of the stages includes a set node, a pull-up switching device for outputting a corresponding scan pulse according to a logic state of the set node, at least two reset nodes, at least two pull-down switching devices, each of the pull-down switching devices being connected to a corresponding reset node to output an off voltage according to a voltage level of the corresponding reset node, and a node controller for controlling logic states of the nodes of a corresponding stage and logic states of the nodes of stages different from the corresponding stage together, wherein the node controllers of the stages control an output order of the scan pulses from the stages according to a forward voltage and reverse voltage having opposite phases.

Abstract: A liquid crystal display device includes a driving circuit provided with a switching device on a liquid crystal display panel, the switching device including a plurality of thin film transistors connected in parallel and commonly interconnected using a gate electrode.

Abstract: A liquid crystal display device and a driving method thereof is presented in which a first liquid crystal cell is provided at one side of the data line, and a second liquid crystal cell is provided at the other side thereof. A first switching part is provided for each first liquid crystal cell positioned at an ith horizontal line (wherein i is an integer) to be controlled by the (i?1)th gate line and the ith gate line. A second switching part is provided for each second liquid crystal cell positioned at an ith horizontal line to be controlled by the ith gate line.

Abstract: A liquid crystal display device includes a driving circuit provided with a switching device on a liquid crystal display panel, the switching device including a plurality of thin film transistors connected in parallel and commonly interconnected using a gate electrode.

Abstract: A liquid crystal display device and a driving method thereof is presented in which a first liquid crystal cell is provided at one side of the data line, and a second liquid crystal cell is provided at the other side thereof. A first switching part is provided for each first liquid crystal cell positioned at an ith horizontal line (wherein i is an integer) to be controlled by the (i?1)th gate line and the ith gate line. A second switching part is provided for each second liquid crystal cell positioned at an ith horizontal line to be controlled by the ith gate line.