Abstract: Discussed herein is a shift register which is capable of stabilizing an output thereof. The shift register includes a plurality of stages for sequentially outputting scan pulses in such a manner that high durations of the scan pulses partially overlap with each other. Each of the stages includes a node controller for controlling a charging duration of a set node, and an output unit for outputting a corresponding one of the scan pulses through an output terminal for the charging duration of the set node.

Abstract: A display device and driving method are provided. A display device includes a display area that includes a plurality of pixel cells in respective pixel regions defined by a plurality of gate and data lines crossing each other. A data driver is operable to supply data signals to the pixel cells. The pixel cells are connected with the first data line and are divided into a plurality of pixel-cell groups. The data driver is operable to supply the data signal of first polarity to the pixel cells included in the odd-numbered pixel-cell groups, and to supply the data signal of second polarity to the pixel cells included in the even-numbered pixel-cell groups. The first polarity is opposite to the second polarity. A shift register that is operable to drive the gate lines to supply the scan pulses of different amplitudes to neighboring pixel cells included in the different pixel-cell groups.

Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.

Abstract: A shift register includes a plurality of stages for sequentially outputting scan pulses to drive a plurality of gate lines, wherein each of the stages includes a set node, a pull-up switching device for outputting a corresponding scan pulse according to a logic state of the set node, at least two reset nodes, at least two pull-down switching devices, each of the pull-down switching devices being connected to a corresponding reset node to output an off voltage according to a voltage level of the corresponding reset node, and a node controller for controlling logic states of the nodes of a corresponding stage and logic states of the nodes of stages different from the corresponding stage together, wherein the node controllers of the stages control an output order of the scan pulses from the stages according to a forward voltage and reverse voltage having opposite phases.

Abstract: A gate driving circuit includes a first clock generator to output n output control clock pulses having different phases; a second clock generator to create m*n output clock pulses having different phases and partially overlapped with one another in high periods thereof, to arrange the m*n output clock pulses in sequence of phase, to bind the m*n output clock pulses arranged in sequence of phase in units of n to generate m groups, each of which has n output clock pulses, and to output the m*n output clock pulses so that a rising edge of an output clock pulse having a k-th sequence of phase included in each group is located in a high period of an output control clock pulse having a k-th sequence of phase among the n output control clock pulses; and a shift register sequentially outputting a plurality of scan pulses.

Abstract: Disclosed herein is a shift register in which leakage of charges from a voltage at a set node is prevented to stabilize an output from a stage. The shift register includes a plurality of stages for sequentially outputting scan pulses. Each stage includes a node controller for controlling signal states of a set node and a reset node, and an output unit supplied with any one of a plurality of clock pulses having different phases. The output unit outputs the supplied clock pulse as a scan pulse through an output terminal thereof according to the signal states of the set node and reset node. The node controller includes a first discharging switching device which is turned on or off in response to a scan pulse from a downstream stage. The first discharging switching device is connected between any one of a plurality of clock transfer lines and the set node.

Abstract: A gate driving apparatus for a liquid crystal display panel with liquid crystal cells, thin film transistors, gate lines, and data lines includes a plurality of shift registers on the liquid crystal display panel to apply scanning signals to the gate lines, and a gate driving integrated circuit connected to the liquid crystal display panel to generate a plurality of control signals for controlling the shift registers.

Abstract: A display device and driving method are provided. A display device includes a display area that includes a plurality of pixel cells in respective pixel regions defined by a plurality of gate and data lines crossing each other. A data driver is operable to supply data signals to the pixel cells. The pixel cells are connected with the first data line and are divided into a plurality of pixel-cell groups. The data driver is operable to supply the data signal of first polarity to the pixel cells included in the odd-numbered pixel-cell groups, and to supply the data signal of second polarity to the pixel cells included in the even-numbered pixel-cell groups. The first polarity is opposite to the second polarity. A shift register that is operable to drive the gate lines to supply the scan pulses of different amplitudes to neighboring pixel cells included in the different pixel-cell groups.

Abstract: The present invention relates to an instrument connection type unit pack combined cell cartridge assembled into a compound cell interconnection mesh, and to a combined cartridge electricity storage device assembled into a compound unit interconnection mesh in which a plurality of cell cartridges are electrically interconnected. The unit pack combined cell cartridge of the present invention is configured such that a plurality of cells are interconnected into a unit pack using a suitable device (bus bar), and a plurality of unit packs are interconnected into a unitary cartridge using a suitable device (intermediate conductor plate). The combined cartridge electricity storage device of the present invention is configured such that a plurality of unit pack combined cartridges are accommodated in an outer case and interconnected into a serial or parallel compound interconnection structure to form a unitary system.

Abstract: A liquid crystal display device and a driving method thereof is presented in which a first liquid crystal cell is provided at one side of the data line, and a second liquid crystal cell is provided at the other side thereof. A first switching part is provided for each first liquid crystal cell positioned at an ith horizontal line (wherein i is an integer) to be controlled by the (i?1)th gate line and the ith gate line. A second switching part is provided for each second liquid crystal cell positioned at an ith horizontal line to be controlled by the ith gate line.

Abstract: A display device and driving method are provided. A display device includes a display area that includes a plurality of pixel cells in respective pixel regions defined by a plurality of gate and data lines crossing each other. A data driver is operable to supply data signals to the pixel cells. The pixel cells are connected with the first data line and are divided into a plurality of pixel-cell groups. The data driver is operable to supply the data signal of first polarity to the pixel cells included in the odd-numbered pixel-cell groups, and to supply the data signal of second polarity to the pixel cells included in the even-numbered pixel-cell groups. The first polarity is opposite to the second polarity. A shift register that is operable to drive the gate lines to supply the scan pulses of different amplitudes to neighboring pixel cells included in the different pixel-cell groups.

Abstract: A shift register includes a plurality of first to n-numbered stages, where n is a positive integer. Each stage includes a node controller controlling respective voltages of a first node and a second node in accordance with an output signal from the (i?j1)-numbered stage and an output signal from the (i+j2)-numbered stage, wherein i is a positive integer from 1 to n, j1 is a positive integer greater than or equal to 2, and j2 is a positive integer equal to or different from j1; and an output unit outputting one of a plurality of clock signals in accordance with the respective voltages of the first and second nodes.

Abstract: A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.

Abstract: Disclosed herein is a liquid crystal display device which is capable of reducing the number of data drive integrated circuits (ICs) to curtail a production cost. The liquid crystal display device includes a plurality of pixel cells formed respectively in areas defined by a plurality of gate lines and a plurality of data lines, a first unit pixel including at least three of the pixel cells, the at least three pixel cells being connected to different ones of the data lines, and a second unit pixel including at least three of the pixel cells other than the at least three pixel cells of the first unit pixel, the at least three pixel cells of the second unit pixel being connected respectively to the different data lines to which the at least three pixel cells of the first unit pixel are connected, wherein the first and second unit pixels are arranged in a direction of the data lines and connected to different ones of the gate lines.

Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.

Abstract: A liquid crystal display (LCD) device comprises a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and data lines, each pixel region associated with a thin film transistor, a gate driving unit having an amorphous semiconductor and integrally formed with the liquid crystal panel capable of sending a scan signal to the gate lines having a pulse width longer than a turned on time of the thin film transistor located within the pixel region, and a data driving unit connected to the data lines capable of sending an image signal to the data lines.

Abstract: A shift register includes a plurality of first to n-numbered stages, where n is a positive integer. Each stage includes a node controller controlling respective voltages of a first node and a second node in accordance with an output signal from the (i?j1)-numbered stage and an output signal from the (i+j2)-numbered stage, wherein i is a positive integer from 1 to n, j1 is a positive integer greater than or equal to 2, and j2 is a positive integer equal to or different from j1; and an output unit outputting one of a plurality of clock signals in accordance with the respective voltages of the first and second nodes.

Abstract: A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.

Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.

Abstract: An active matrix type display device is disclosed, to reduce a fabrication cost, which comprises first to third gate lines arranged at one direction; first and second data lines arranged orthogonally to the first to third gate lines; a first pixel cell connected to the first gate line and the first data line; a second pixel cell connected to the first gate line and the second data line; a third pixel cell connected to the second gate line and the first data line; a fourth pixel cell connected to the second gate line and the second data line; a fifth pixel cell connected to the third gate line and the first data line; and a sixth pixel cell connected to the third gate line and the second data line, wherein the three predetermined pixel cells of displaying the different colors among the first to sixth pixel cells constitute a first unit pixel for displaying a first unit image; and the three other pixel cells except the pixel cells included in the first unit pixel constitute a second unit pixel for displaying a