Abstract: A shift register is disclosed, which can prevent malfunctioning of device by decreasing the load on a discharging voltage source line, and can decrease a size of stage. The shift register comprises a plurality of stages to sequentially output scan pulses through respective output terminals, wherein each of the stages comprises a pull-up switching unit controlled based on a signal state of node, and connected between the output terminal and any one among a plurality of clock transmission lines to transmit the clock pulses provided with sequential phase differences; and a node controller to control the signal state of node, and to discharge the node by using the clock pulse from any one among the plurality of clock transmission line.

Abstract: An active matrix display device includes: a display panel; a gate driver; and a data driver, wherein the gate driver includes a plurality of shift registers to output signals that are sequentially shifted, each of the shift registers including: a first control part for controlling a first node in response to a first clock signal; a second control part for controlling second and third nodes in response to the start signal and a second clock signal; and an output part to selectively output one of a third clock signal and a first supply voltage in response to voltages of the first, second, and third nodes, whereby second and third supply voltages, which are different from each other, are switched for application at the second and third nodes.

Abstract: A liquid crystal display device includes a liquid crystal panel having a pixel region, a graphic interface unit generating a first data enable signal having first and second time intervals, a signal modulating unit generating a second data enable signal by using the first data enable signal, the second data enable signal having third and fourth time intervals, and a timing controller generating the data signals by using the second data enable signal, wherein data signals are not input to the pixel region during the third time interval and are input to the pixel region during the fourth time interval, and the forth time interval is shorter than the second time interval.

Abstract: A shift register structure comprising a shift register for sequentially outputting voltages as a clock signal and a start voltage are inputted thereto, and a cleaner means connected to the shift register for removing noise within the start voltage. The cleaner means is a transistor for inputting a clock signal to a gate and for inputting a signal outputted from the shift register to a source.

Abstract: A shift register has a plurality of stages which output driving signals, each stage including a pull-up transistor to output a first clock signal in response to a logic value of a Q node; a pull-down transistor to supply a voltage from a first voltage supply source to the output in response to a logic value of a Qb node; a Q node controller to control the logic value of the Q node in response to any one of the previous stage's output signal and the next stage's output signal; and a Qb node controller to control the logic value of the Qb node to alternate repeatedly between low and high by use of at least one of a second clock signal, a third clock signal and the logic value of the Q node when the output signal is in a low state.

Abstract: A shift register which is capable of performing bi-directional scanning is disclosed. The shift register includes first and second voltage input lines to which first and second voltages are input, respectively with the phases of the first and second voltages being opposite to each other; a plurality of stages dependently connected to a plurality of clock signal input lines which input a plurality of clock signals whose phases are sequentially delayed, wherein each stage includes: a scan direction controller to selectively output the first and second voltages thereto, according to first and second start pulses, and for controlling scan direction, a node controller to control voltages of first and second nodes according to a signal output from the scan direction controller, and an output unit to output a clock signal from one of the plurality of clock signal input lines thereto according to the voltage of each of the first and second nodes.

Abstract: A display device includes a substrate with a display area having gate lines and data lines defining cells that each has a pixel electrode, a driving circuit on the substrate, at least one first signal line including lower and upper lines overlapping each other with an insulation layer interposed therebetween, the first signal line adjacent to the driving circuit, and at least one second signal line to connect the first signal line to the driving circuit.

Abstract: A display device and driving method are provided. A display device includes a display area that includes a plurality of pixel cells in respective pixel regions defined by a plurality of gate and data lines crossing each other. A data driver is operable to supply data signals to the pixel cells. The pixel cells are connected with the first data line and are divided into a plurality of pixel-cell groups. The data driver is operable to supply the data signal of first polarity to the pixel cells included in the odd-numbered pixel-cell groups, and to supply the data signal of second polarity to the pixel cells included in the even-numbered pixel-cell groups. The first polarity is opposite to the second polarity. A shift register that is operable to drive the gate lines to supply the scan pulses of different amplitudes to neighboring pixel cells included in the different pixel-cell groups.

Abstract: A gate driver includes a plurality of stage groups, a gate driving circuit, and an output controller. The gate driving circuit supplies the plurality of stage groups with a plurality of clock pulses. The plurality of stage groups supply the input clock pulses to associated gate lines of a liquid crystal panel. The output controller generates a plurality of control voltage signals that control which of the plurality of stage groups generate an output signal.

Abstract: A liquid crystal display (LCD) device comprises a liquid crystal panel having a plurality of pixel regions defined by a plurality of gate lines and data lines, each pixel region associated with a thin film transistor, a gate driving unit having an amorphous semiconductor and integrally formed with the liquid crystal panel capable of sending a scan signal to the gate lines having a pulse width longer than a turned on time of the thin film transistor located within the pixel region, and a data driving unit connected to the data lines capable of sending an image signal to the data lines.

Abstract: A shift register structure comprising a shift register for sequentially outputting voltages as a clock signal and a start voltage are inputted thereto, and a cleaner means connected to the shift register for removing noise within the start voltage. The cleaner means is a transistor for inputting a clock signal to a gate and for inputting a signal outputted from the shift register to a source.

Abstract: A driving circuit for a flat panel display device includes shift register stages, each containing: a first TFT charging a Q node according to a start signal; a second TFT discharging the Q node according to an output voltage of a next shift register stage; a pull-up unit increasing an output voltage according to the Q node voltage; an odd pull-down unit decreasing the output voltage in an odd frame according to a QB-o node voltage; and an even pull-down unit decreasing the output voltage in an even frame according to a QB-e node voltage. A gate and drain of a third odd TFT connected to the QB-o node are connected to each other and receive an odd source voltage. A gate and drain of the third even TFT connected to the QB-e node are connected to each other and receive an even source voltage.

Abstract: A driving circuit for a flat panel display device includes a generation unit for generating n-phase form generation clocks; and a plurality of shift register stages for sequentially generating a plurality gate signals to a plurality of gate lines using the n-phase form generation clocks, one of the shift register stage including first and second output terminals for outputting first and second switching signals, respectively, using an output signal of one of the preceding shift register stages and an output signal of one of the subsequent shift register stages; a first transistor connected to the first output terminal for receiving one of the n-phase form generation clocks; and a second transistor connected to the second output terminal and the first transistor, wherein each gate line is connected to a node between the first and second transistors.

Abstract: A driving circuit for a flat panel display device includes first and second generation units generating m-phase circulation enable control clocks and n-phase circulation form generation clocks; and a plurality of shift register stages generating output signals by using the m-phase circulation enable control clocks and the n-phase circulation form generation clocks. Each shift register stage includes an input terminal receiving the m-phase circulation enable control clocks; first and second nodes outputting first and second signals, respectively, using the m-phase circulation enable control clocks; a first transistor connected to the first node and receiving the n-phase circulation form generation clocks; a second transistor connected to the second node and the first transistor; and an output terminal between the first and second transistors and outputting one of the output signals.

Abstract: A liquid crystal display device includes a driving circuit provided with a switching device on a liquid crystal display panel, the switching device including a plurality of thin film transistors connected in parallel and commonly interconnected using a gate electrode.

Abstract: A liquid crystal display device includes a liquid crystal panel having a pixel region, a graphic interface unit generating a first data enable signal having first and second time intervals, a signal modulating unit generating a second data enable signal by using the first data enable signal, the second data enable signal having third and fourth time intervals, and a timing controller generating the data signals by using the second data enable signal, wherein data signals are not input to the pixel region during the third time interval and are input to the pixel region during the fourth time interval, and the forth time interval is shorter than the second time interval.

Abstract: A reflectance-type liquid crystal display device includes a first light scattering unit on a first substrate, a reflecting layer having a second light scattering unit on a second substrate, and a liquid crystal layer between the two substrates. One of the two light scattering units defines a regular-directional scattering unit which can easily control the reflectance characteristics, and the other light scatterin unit defines a random-directional scattering unit which prevents the light interference caused by the regular-directional scattering unit.