Abstract: A substrate includes a power plane and a ground plane that are placed apart from and are substantially parallel to each other, and at least one signal line that is placed between the power plane and the ground plane. The ground plane includes a first conductive layer having a first conductivity. The power plane includes a second conductive layer having the first conductivity, and the power plane or the ground plane includes a third conductive layer having a second conductivity lower than the first conductivity. The third conductive layer faces the at least one signal line across a dielectric substance.

Abstract: The present invention provides a method for determining in a pharmaceutical test formulation the presence or absence of a peptide compound PYY3-36 represented by the following amino acid sequence: H-Ile-Lys-Pro-Glu-Ala-Pro-Gly-Glu-Asp-Ala-Ser-Pro-Glu-Glu-Leu-Asn-Arg-Tyr-Tyr-Ala-Ser-Leu-Arg-His-Tyr-Leu-Asn-Leu-Val-Thr-Arg-Gln-Arg-Tyr-X (SEQ ID NO: 1), wherein X is OH or a carboxy acid-protecting group, the method comprising (1) preparing a solution by mixing the pharmaceutical test formulation with cucurbit[7]uril in a solvent; and (2) thermally analyzing the solution prepared in Step (1).

Abstract: Provided is a method of aging black garlic, which in an embodiment involved the following procedures: classifying the garlic according to its condition and pre-treating it to achieve clean appearance; sealing the garlic in a vinyl pack by 10 kg and storing it in a tray; putting said tray in an aging device for a black garlic, applying steam and heat for 1˜3 hrs while maintaining a temperature of 80˜100° C. inside the aging device, and treating by steam under a high temperature and high humidity condition; main aging by applying steam and heat to the treated garlic for 198 hrs while maintaining a temperature of 72˜78° C. inside the aging device; after-aging by applying steam and heat to the garlic, which had undergone main aging process, for 35 hrs while maintaining 60˜69° C. temperature inside the aging device; drying the after-aged garlic for 51 hrs while maintaining a temperature of 50˜58° C.

Abstract: The present invention provides a method for determining in a pharmaceutical test formulation the presence or absence of a peptide compound PYY3-36 represented by the following amino acid sequence: H-Ile-Lys-Pro-Glu-Ala-Pro-Gly-Glu-Asp-Ala-Ser-Pro-Glu-Glu-Leu-Asn-Arg-Tyr-Tyr-Ala-Ser-Leu-Arg-His-Tyr-Leu-Asn-Leu-Val-Thr-Arg-Gln-Arg-Tyr-X (SEQ ID NO: 1), wherein X is OH or a carboxy acid-protecting group, the method comprising (1) preparing a solution by mixing the pharmaceutical test formulation with cucurbit[7]uril in a solvent; and (2) thermally analyzing the solution prepared in Step (1).

Abstract: A memory module having a start-type topology and a method of fabricating the same are provided. The memory module includes a substrate. Memory devices are mounted on the substrate in at least two rows and at least two columns. A star-type topology is disposed to be electrically connected to the memory devices. One or more pairs of adjacent ones of the memory devices have a point-symmetric structure.

Abstract: The present invention provides a method for quantifying a peptide compound having a phenylalanine residue at the N-terminal, comprising measuring the content of heat generated by mixing 1) a peptide compound having a phenylalanine residue at the N-terminal, 2) cucurbit[7]uril, and 3) a metal ion in a solution.

Abstract: A semiconductor structure may be formed by a wet etching process using an etchant containing water. The semiconductor structure may include a plurality of patterns having an increased or higher aspect ratio and may be arranged closer to one another. A dry cleaning process may be performed using hydrogen fluoride gas on the semiconductor structure.

Abstract: In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract: Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.

Abstract: In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

Abstract: In a phase-change semiconductor device and methods of manufacturing the same, an example method may include forming a metal layer pattern on a substrate, the metal layer pattern including an opening that exposes a portion of the substrate, forming an etch stop layer on the metal layer pattern, a sidewall of the opening and the exposed portion of the substrate, the etch stop layer formed with a thickness less than an upper thickness threshold, and reducing at least a portion of the etch stop layer, the reduced portion of the etch stop layer forming an electrical connection with the substrate.

Abstract: In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.

Abstract: A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.

Abstract: The present invention provides a method for determining in a pharmaceutical test formulation the presence or absence of a peptide compound PYY3-36 represented by the following amino acid sequence: H-Ile-Lys-Pro-Glu-Ala-Pro-Gly-Glu-Asp-Ala-Ser-Pro-Glu-Glu-Leu-Asn-Arg-Tyr-Tyr-Ala-Ser-Leu-Arg-His-Tyr-Leu-Asn-Leu-Val-Thr-Arg-Gln-Arg-Tyr-X (SEQ ID NO: 1), wherein X is OH or a carboxy acid-protecting group, the method comprising (1) preparing a solution by mixing the pharmaceutical test formulation with cucurbit[7]uril in a solvent; and (2) thermally analyzing the solution prepared in Step (1).

Abstract: Disclosed herein is a system for managing chemicals using Radio-Frequency Identification (RFID). A storage facility identification tag, attached to a chemical storage facility in a laboratory, stores the unique identification code of the chemical storage facility and a list of chemicals. A chemical identification tag, attached to the cover of a chemical container, stores the unique identification code of the chemical storage facility and chemical-related information. A mobile terminal, provided with an RFID reader, receives and outputs the unique identification code of the chemical storage facility, the list of the chemicals, and the chemical-related information.

Abstract: Example embodiments of the present invention relate to an electrode structure, a method of manufacturing the electrode structure, a phase-change memory device having the electrode structure and a method of manufacturing the phase-change memory device. The electrode structure may include a pad, a first insulation layer pattern, a second insulation layer pattern and/or an electrode. The first insulation layer pattern may be formed on the pad. The first insulation layer pattern may have a first opening that partially exposes the pad. The second insulation layer pattern may be formed on the first insulation layer pattern. The second insulation layer pattern may have a second opening connected to the first opening. The electrode may be formed on the pad and filling the first and the second openings.

Abstract: Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present invention relate to an etching solution having an etching selectivity between a polysilicon layer and an oxide layer, a method of forming a pattern using an etching solution using the same, a method of manufacturing a multiple gate oxide layer using the same, and a method of manufacturing a flash memory device using the same. An etching solution including hydrogen peroxide (H2O2) and ammonium hydroxide (NH4OH) by a volume ratio of about 1:2 to about 1:10 mixed in water. In a method of forming a pattern and methods of manufacturing a multiple gate oxide layer and a flash memory device, a polysilicon layer may be formed on a substrate.

Abstract: A method of forming a recess channel trench pattern for forming a recess channel transistor is provided. A mask layer is formed on a semiconductor substrate, which is then patterned to expose an active region and a portion of an adjacent device isolating layer with an isolated hole type pattern. Using this mask layer the semiconductor substrate and the device isolating layer portion are selectively and anisotropically etched, thereby forming a recess channel trench with an isolated hole type pattern. The mask layer may be patterned to be a curved line type. In this case, the once linear portion is curved to allow the device isolating layer portion exposed by the patterned mask layer to be spaced apart from an adjacent active region. The semiconductor substrate and the device isolating layer portion are then etched, thereby forming a recess channel trench with a curved line type pattern.