Abstract: In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

Abstract: Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.

Abstract: For planarizing an IC (integrate circuit) material, a first slurry is dispensed for a first planarization of the IC material using the first slurry, and a second slurry is dispensed for a second planarization of the IC material using the second slurry. The first and second slurries are different. For example, the first slurry is silica based for faster planarization during the first planarization. Thereafter, the second planarization is performed with the second slurry that is ceria based with higher planarity for attaining sufficient planarization of the IC material.

Abstract: A wafer guide includes a horizontal support panel and at least three vertical panels attached on one surface of the support panel. Each of the vertical panels has a vertical body panel and a plurality of protrusions upwardly extended from a top surface of the vertical body panel. Gap regions between the protrusions act as slots for holding wafers. Sidewalls of the slots have a convex shaped profile when viewed from a top view, and bottom surfaces of the slots also have a convex shaped profile when viewed from a cross sectional view that crosses the vertical panels.

Abstract: A semiconductor device and a method thereof are disclosed. In the example method, a mold layer having an opening may be formed on a substrate. A conductive etchable pattern (e.g., a preliminary conductive pattern, a lower electrode pattern, etc.) may be formed within the opening. The mold layer may be reduced so as to expose a portion of the conductive etchable pattern and less than all of the exposed portion of the conductive etchable pattern may be etched such that the etched conductive etchable pattern has a reduced thickness. The example semiconductor device may include the etched conductive etchable pattern as above-described with respect to the example method.

Abstract: Disclosed is an organic stripping composition and a method of etching a semiconductor device in which the generation of an Si pitting phenomenon can be prevented. The composition includes a compound including a hydroxyl ion (OH?), a compound including a fluorine ion (F?) and a sufficient amount of an oxidizing agent to control the pH of the composition within the range of from about 6.5 to about 8.0. The method includes dry etching an oxide by a dry etching using a plasma, and then ashing the etched oxide using an ashing process to remove an organic material. The method further includes supplying the organic stripping composition to remove residues including any residual organic material, a metal polymer, and an oxide type polymer. The stripping composition is stable onto various metals and does not induce the Si pitting phenomenon.

Abstract: A wafer guide includes a horizontal support panel and at least three vertical panels attached on one surface of the support panel. Each of the vertical panels has a vertical body panel and a plurality of protrusions upwardly extended from a top surface of the vertical body panel. Gap regions between the protrusions act as slots for holding wafers. Sidewalls of the slots have a convex shaped profile when viewed from a top view, and bottom surfaces of the slots also have a convex shaped profile when viewed from a cross sectional view that crosses the vertical panels.

Abstract: A method of forming an epitaxial contact plug in a semiconductor device comprises forming an insulating interlayer on a semiconductor substrate, forming a mushroom-shaped epitaxial plug in an opening of the insulating interlayer, forming a buffer layer on the epitaxial plug and the insulating interlayer, and planarizing epitaxial plug and the insulating interlayer using a chemical mechanical polishing (CMP) process.

Abstract: In a slurry composition preventing damage to an insulation layer, and uniformly polishing a metal layer, the slurry composition includes an acidic aqueous solution having a first pH and an anionic surfactant having a second pH lower than or equal to the first pH. Irregular polishing of the metal layer relative to a pattern density may be prevented and a contact having a uniform thickness may be formed using the slurry composition.

Abstract: A method of fabricating a semiconductor device including sequentially forming a polysilicon layer, a first insulating layer, and a photoresist layer over a gate oxide film positioned on a semiconductor substrate. A photoresist pattern with a first groove is formed by selectively patterning the photoresist layer to partially expose a surface of the first insulating layer. A second insulating layer is formed over the photoresist pattern with the first groove and over the exposed surface of the first insulating layer. A sacrificial spacer is formed on each inner wall of the first groove by etching back the second insulating layer and forming a second groove in the first insulating layer in communication with the first groove to expose a surface of the polysilicon layer at the bottom of the second groove. The photoresist pattern is removed, and an arbitrary layer pattern is formed over the polysilicon layer at the bottom of the second groove.

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract: A method of forming a capacitor can include forming a protective layer on a metal layer in a trench in an insulating layer and outside thereof. A surface of the protective layer and the metal layer beneath can be planarized using a chemical mechanical polishing (CMP) process to expose a surface of the insulating layer outside the trench. Related structures are also disclosed.

Abstract: An isolation layer having a first depth is formed from an upper face of a substrate. Source/drain regions including junctions are formed in the substrate. Each of the junctions has a second depth substantially smaller than the first depth. A first recess is formed in the substrate by a first etching process. A protection layer pattern is formed on a sidewall of the first recess. A second recess is formed beneath the first recess. The second recess has a width substantially larger than that of the first recess. The second recess is formed by a second etching process using an etching gas containing an SF6 gas, a Cl2 gas and an O2 gas. A gate insulation layer is formed on surfaces of the first and the second recesses. The second recess having an enlarged shape may reduce a width of the junction between the gate electrode and the isolation layer so that a leakage current generated through the junction may decrease.

Abstract: A platen structure of a polishing apparatus for semiconductor wafer and a method for exchanging a polishing pad affixed to the same are provided in which the polishing pad supported by the platen is exchanged with convenience within a short time. The platen structure of the polishing apparatus in which the polishing pad attached to the platen of the polishing apparatus comprises a pad plate to which the polishing pad for polishing a wafer is attached, and a platen body combined with the pad plate and having at least one vacuum hole formed thereto to provide a vacuum passage.

Abstract: The present invention discloses a multi-function interface card. The multi-function interface card comprises a central processor mounted on a PCB (printed circuits board). A communication module is coupled to the central processor. An arbitrator is coupled to the central processor. An interface is coupled to the arbitrator to act as I/O for exchanging signal between the multi-function interface card and an external device. A plurality of switches are included, wherein each one of the plurality of switches is coupled to the arbitrator respectively. A plurality of controllers are included, wherein each one of the plurality of controllers is coupled to corresponding one of the plurality of switches respectively. The arbitrator is capable of recognizing a configuration access from an input signal received by the arbitrator and to determine which one switch of the plurality of switches is turned off thereby allowing the corresponding function controller to respond to the data access.

Abstract: A chemical supply system includes at least two supply pipes for supplying at least two different chemicals; a mixing unit connected to the supply pipes for mixing at least two different chemicals to form a chemical mixture, an exhausting unit for exhausing the chemical mixture externally; and a filtering unit provided between the mixing unit and the exhausting unit for filtering the chemical mixture to prevent chemical particles having more than a predetermined size from being exhausted.

Abstract: A wafer guide used in cleaning and/or drying processes of semiconductor wafers is provided. The wafer guide includes a horizontal support panel and at least three vertical panels attached on one surface of the support panel. Each of the vertical panels has a vertical body panel and a plurality of protrusions upwardly extended from a top surface of the vertical body panel. Gap regions between the protrusions act as slots for holding wafers. Sidewalls of the slots have a convex shaped profile when viewed from a top view, and bottom surfaces of the slots also have a convex shaped profile when viewed from a cross sectional view that crosses the vertical panels. Accordingly, contact areas between the wafers and the wafer guide are reduced to improve a drying efficiency of the wafers.

Abstract: A slurry composition includes about 4.25 to about 18.5 weight percent of an abrasive, about 80 to about 95 weight percent of deionized water, and about 0.05 to about 1.5 weight percent of an additive. The slurry composition may further include a surfactant. In a polishing method using the slurry composition, a polysilicon layer may be rapidly polished, and also dishing and erosion of the polysilicon layer may be suppressed.

Abstract: An apparatus for polishing a wafer is provided. The apparatus comprises a polishing pad for polishing the wafer. The polishing pad is divided into multiple portions that are rotated in a substantially same direction. At least one of the portions of the polishing pad is adapted to rotate at a speed different than the other portions. A driving unit is also provided for moving the polishing pad. A polishing head is employed for maintaining the side of the wafer to be polished engaged with the polishing pad, for contacting the polished surface of the wafer with the polishing pad, and for rotating the wafer.

Abstract: Methods of manufacturing a semiconductor device are provided. A trench is formed in a semiconductor substrate. A first field oxide layer is formed that partially fills the trench. The first field oxide layer defines an active region of the substrate that is adjacent to the trench. An upper portion of sidewalls of the trench extends upward beyond a surface of the first field oxide layer. A first liner is formed on the first field oxide layer and on the portion of the sidewalls of the trench that extend upward beyond the first field oxide layer. A second field oxide layer is formed on the first liner and fills the trench. The second field oxide layer and the first liner are each partially removed to expose a top adjacent surface and upper sidewalls of the trench along the active region of the substrate. A dielectric layer is formed on the exposed top adjacent surface and upper sidewalls of the trench. A gate electrode is formed on the dielectric layer.