Abstract: The present invention relates to an improved method for manufacturing a crystalline layered sodium disilicate and more particularly, to the improved method for manufacturing the crystalline layered sodium disilicate comprising the steps including the preparation of granules in a certain ratio of anhydrous sodium silicate cullet, a starting material, in the presence of some binders such as water and an aqueous solution of sodium silicate, followed by a crystallization step of the granules, thus ensuring that a small amount of final product is recycled to the prior crystallization step in order to prevent the attachment of granules to an inner crystallization device, which occurs due to local sintering in a high-temperature crystallization condition of continual process and also to further enhance the unit productivity during the mass production of crystalline layered sodium disilicate.

Abstract: Disclosed is a non-volatile semiconductor memory device including a circuit for controlling potentials of select lines and word lines in accordance with bit line setup, string select line setup, program and discharge periods of a program cycle. The control circuit biases a string select line to a power supply voltage during the bit line setup period in the program cycle, and to a voltage between the power supply voltage and ground voltage during the string select line setup and the program periods. According to the string select line control scheme, program disturb due to a noise voltage induced at a string select line when a program voltage is applied to a word line adjacent to the string select line is prevented.

Abstract: The present invention relates to a process for preparing a highly active metallocene catalyst supported on polymer bead for olefin polymerization, a metallocene catalyst prepared by the said process and a method for alkylene polymerization by employing the said catalyst. The process for preparing a highly active metallocene catalyst supported on polymer bead for olefin polymerization which comprises the steps of: dissolving divinylbenzene, vinylbenzylchloride, and an initiator in an organic solvent, mixing it with a suspension stabilizer of aqueous phase, and carrying out suspension-polymerization at the temperature of 40 to 80° C. to obtain polystyrene; swelling the polystyrene in dialcoholamine dissolved in an organic solvent at ambient temperature for 1 to 3 days, to give a polymer having a functional group of dialcoholamine; and, reacting the polymer with a metallocene compound (CpM*Cl3) dissolved in an organic solvent.

Abstract: The present invention relates to a multiple output crystal oscillator having a plurality of output terminals for implementing multiple output and Integrated Circuit (IC) chips. More particularly, the crystal oscillator comprises a crystal resonator, a first IC chip having an oscillating circuit block and a frequency-adjusting circuit block, a second IC chip having an output-adjusting block, and a substrate structure for mounting said first and second IC chips, wherein said output terminals include a basic output terminal for outputting the oscillating signal from said first IC chip and at least one additional output terminal for outputting at least one wave form-adjusted oscillation signal from said second IC chip. In the present invention, said basic output terminal is placed on one of four underside corners of said substrate, and said additional output terminal is placed on the portion of the underside except the corners.

Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

Abstract: A temperature compensated crystal oscillator has first and second layered structures, an IC chip, a crystal vibrating chip, a resin mold portion and a metal cover. Each of the first and second layered structures has a cavity formed therein. The cavity formed in the second layered structure does not overlap with the cavity of the first layered structure. The IC chip is inserted into the cavity of the first layered structure. The crystal vibrating chip is inserted into the cavity of the second layered structure. The resin mold portion is formed by charging resin into the cavity of the first layered structure. The metal cover is arranged on the upper surface of the second layered structure for covering an opening of the cavity of the second layered structure.

Abstract: A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area.

Abstract: Disclosed herein is a temperature compensated crystal oscillator. The temperature compensated crystal oscillator has first and second layered structures, an IC chip, a crystal vibrating chip, a resin mold portion and a metal cover. The first layered structure is comprised of at least one layer and provided with a cavity formed therein. The second layered structure is arranged on the upper surface of the first layered structure, comprised of at least one layer, and provided with a cavity formed in a region not overlapped with the cavity of the first layered structure. The IC chip is inserted into the cavity of the first layered structure. The crystal vibrating chip is inserted into the cavity of the second layered structure. The resin mold portion is formed by charging resin into the cavity of the first layered structure accommodating the IC chip to form its bottom surface level with the lower surface of the first layered structure.

Abstract: Disclosed is a method of fabricating fringe field switching mode liquid crystal display by forming a gate bus line and a common electrode line on a lower substrate in parallel with each other; forming a gate insulating layer on the lower substrate; forming a counter electrode on the gate insulating layer to overlap with a predetermined part of the common electrode line; depositing a metal layer on the resulting lower substrate and then selectively patterning the metal layer, thereby forming a contacting part connecting the counter electrode to the exposed common electrode line; depositing a protective layer on the lower substrate obtained after formation of the source, the drain and the contacting part; selectively etching the protective layer to expose a predetermined part of the drain; and forming a pixel electrode on the protective layer to form a field with the counter electrode, being in contact with the drain.

Abstract: A positive active material for a rechargeable lithium battery is provided. The positive active material comprises a lithiated intercalation compound and a coating layer formed on the lithiated intercalation compound.

Abstract: The present invention relates to a process for preparing a highly active metallocene catalyst supported on polymer bead for olefin polymerization, a metallocene catalyst prepared by the said process and a method for alkylene polymerization by employing the said catalyst. The process for preparing a highly active metallocene catalyst supported on polymer bead for olefin polymerization which comprises the steps of: dissolving divinylbenzene, vinylbenzylchloride, and an initiator in an organic solvent, mixing it with a suspension stabilizer of aqueous phase, and carrying out suspension-polymerization at the temperature of 40 to 80° C. to obtain polystyrene; swelling the polystyrene in dialcoholamine dissolved in an organic solvent at ambient temperature for 1 to 3 days, to give a polymer having a functional group of dialcoholamine; and, reacting the polymer with a metallocene compound (CpM*Cl3) dissolved in an organic solvent.

Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.

Abstract: A method of programming a non-volatile semiconductor memory device is provided. The method includes a bitline setup step, a well bias setup step, a program step, and a discharge step. In the bitline setup step, either a ground or power supply voltage is supplied respectively to bitlines according to data bits stored in page buffers, and a pocket P-well area is biased with the ground voltage. In the well bias setup step, the ground voltage applied to the pocket P-well area is cut off to make the second well area attain a floating state. Under such a condition, the pocket P-well area is biased with a coupling voltage, which is lower than the ground voltage, through a coupling capacitance between the pocket P-well area and a common source line, or a coupling capacitance between the pocket P-well area and an N-well area.

Abstract: Disclosed is a non-volatile semiconductor memory device including a circuit for controlling potentials of select lines and word lines in accordance with bit line setup, string select line setup, program and discharge periods of a program cycle. The control circuit biases a string select line to a power supply voltage during the bit line setup period in the program cycle, and to a voltage between the power supply voltage and ground voltage during the string select line setup and the program periods. According to the string select line control scheme, program disturb due to a noise voltage induced at a string select line when a program voltage is applied to a word line adjacent to the string select line is prevented.

Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.

Abstract: A nonvolatile semiconductor memory device has a special test mode and circuitry for counting its own fail bits. During the test mode, test data is stored in the memory, and also in a special expected data buffer. The test data stored in the memory cells are then compared to that stored in the expected data buffer. Where there is no correspondence, fail bits are detected. The lack of correspondence is registered, counted, and output to a data output buffer block.

Abstract: Disclosed is a nonvolatile semiconductor memory device which comprises a controller for controlling block select signal generators. The controller simultaneously activates the block select signal generators in a bit line setup and a recovery period, so that the word lines in each of memory blocks are set to a predetermined voltage (for example, a ground voltage, a power supply voltage, or an intermediate voltage), respectively. According to the control scheme, by attenuating a bouncing of a substrate voltage caused in an instant by means of a capacitive coupling between a bit line and a substrate at a transition of a bit line voltage, there are prevented an under program and a program disturb during a program cycle.

Abstract: Disclosed is a method of fabricating fringe field switching mode liquid crystal display comprising the steps of: forming a gate bus line and a common electrode line on a lower substrate in parallel with each other; forming a gate insulating layer on the lower substrate; forming a counter electrode on the gate insulating layer to overlap with a predetermined part of the common electrode line; depositing a metal layer on the resulting lower substrate and then selectively patterning the metal layer, thereby forming a contacting part connecting the counter electrode to the exposed common electrode line; depositing a protective layer on the lower substrate obtained after formation of the source, the drain and the contacting part; selectively etching the protective layer to expose a predetermined part of the drain; and forming a pixel electrode on the protective layer to form a field with the counter electrode, being in contact with the drain.

Abstract: A method for computing maximum traffic capacitance of a base station using a virtual call in the digital mobile communication system in such a way that an operator at operating terminal for Base Station Manager (BSM) inputs call-set-request instructions using the virtual call to maintain and repair the digital mobile communication system so that traffic state is set between mobile stations in the service area of test base station and a vocoder of a Base Station Controller (BSC) to compute maximum traffic capacitance of the test base station. An operator at operation terminal inputs call set information by operator instruction as much as mobile station numbers to be tested to compute maximum traffic capacitance of the base station. The BSM inputs a virtual call-set-request-instruction by means of a virtual call-set-start-flag.

Abstract: A method for controlling an overload of a digital mobile communication system. The digital mobile communication system has a base transceiver station and a base station controller each of which has a database.