Abstract: A liquid crystal display includes an array pixel including a plurality of pixels arranged in a matrix. The plurality of pixels include a set of pixels including a pair of center pixels adjacent to each other, and a pair of first-color pixels and a pair of second-color pixels obliquely facing each other across the center pixels. Each pixel includes a pixel electrode and a thin film transistor. The liquid crystal display further includes a plurality of gate lines extending in a row direction for transmitting a gate signal to the pixels, and a plurality of data lines extending in a column direction for transmitting data signals to the pixels. The pixels are subject to polarity inversion.

Abstract: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of a substrate on source/drain electrode of a thin film transistor having a semiconductor layer, a gate, source/drain areas and the source/drain electrodes, and a blanket etching process is performed to the organic planarization layer to planarize the inorganic layer. After forming a photoresist pattern on the inorganic layer, an etching process is performed to form a hole coupling a pixel electrode with one of the source/drain electrodes. According to the manufacturing method, the hole may be formed using one mask, thereby simplifying a manufacturing process, and improving an adhesion with the pixel electrode by the inorganic layer formed above.

Abstract: A plasma display device and a method for driving the plasma display device. In a first subfield, a first voltage is alternately applied to the first and second electrodes by applying a first addressing scheme for converting an on-cell to an off-cell for a sustain period. In a second subfield, the off-cell is converted to the light emitting state. Initialization in a reset period is appropriately performed whether a write addressing method or an erase addressing method is used.

Abstract: A pad area and a method of fabricating the same, wherein the pad area is formed on a substrate to contact a chip on glass (COG) or a chip on flexible printed circuit (COF) with the substrate. Changing a lower structure of the pad area increases contact points between conductive balls and an interconnection layer or reduces a step difference between an interconnection layer and a passivation layer to enhance and ensure electrical connection.

Abstract: Memory cells in a memory cell array are erased using an erase operation followed by a post-program operation. In the erase operation, an erase voltage is applied to a plurality of memory cells of the memory cell array. In the post program operation, a program voltage is simultaneously applied to at least two word lines coupled to ones of the plurality of erased memory cells of the memory cell array. Related devices are also discussed.

Abstract: An apparatus of converting three color image signals into four color image signals having a white signal is provided, which includes: a lookup table storing a plurality of white scaling factors and a signal converter selecting a corresponding white scaling factor of the white scaling factors stored in the lookup table based on a white scaling signal from an external, converting the three color image signals into the four color image signals based on the selected white scaling factor. Like this, by converting into the four color image signals using the selected white scaling factor based on the white scaling signal from the external, the white scaling factor may be varied without change of a device in which conversion algorithm is stored, thereby manufacturing cost decreases.

Abstract: The present invention relates to an organic electroluminescent display and a driving method thereof, which divides one frame into a plurality of subframes. Since the present invention divides one frame into several subframes, and drives an organic EL device with the subframes assigned to the upper bits and with the corrected gray data for representing the detailed grays between the basic grays during the subframes assigned to the lower bits, it is possible to represent sufficient number of grays regardless of the unstable luminescence characteristics of an organic EL device.

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by a first pump. However, where the bulk voltage exceeds a predetermined detection voltage, a second pump is further activated in order to lower the bulk voltage.

Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.

Abstract: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

Abstract: Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g.

Abstract: A method for controlling an overload of a digital mobile communication system. The digital mobile communication system has a base transceiver station and a base station controller each of which has a database.

Abstract: Disclosed herein is a Digital Signal Processor (DSP) having reconfigurable data paths necessary for processing for a specific use. The DSP includes a plurality of Arithmetic Logic Units (ALUs), pairs of input multiplexers, an output multiplexer, and a reconfiguration control unit. The plurality of ALUs performs unit operations. Each of the pairs of input multiplexers selects data, which will be input to a corresponding ALU, from among input data directed to operate by an instruction word, and output data of the ALUs. The output multiplexer selects one from among the output data of the ALUs, and outputs the selected output data. The reconfiguration control unit controls the data selections of the output multiplexer and the input multiplexers.

Abstract: A column predecoder includes a buffer unit for inputting all column selection signals, decoder units for decoding an output of the buffer unit and column addresses, and level shifters for shifting voltage levels of column selection signals coupled to gates of the column selection transistors in response to an output of the decoder units. Since a ground voltage is applied to a bitline and a high voltage is applied to all column selection signals during the stress test, the stress test time can be shortened.

Abstract: A flash memory device includes a memory cell array arranged in rows and columns; a pad configured to be supplied with a high voltage from the exterior during a stress test operation; a column decoder configured to select a part of the columns in response to column selection signals; and a column predecoder configured to generate the column selection signals in response to an all column selection signal and a column address. The column predecoder simultaneously drives the column selection signals with the high voltage from the pad when the all column selection signal is activated during the stress test operation.

Abstract: The present invention relates to a zirconium based alloy composite having an excellent creep resistance and, more particularly, to a zirconium based alloy composite finally heat-treated to have the degree of recrystallization in the range of 40˜70% in order to improve the creep resistance. The zirconium based alloy comprises 0.8˜1.8 wt. % niobium (Nb); 0.38˜0.50 wt. % tin (Sn); one or more elements selected from 0.1˜0.2 wt. % iron (Fe), 0.05˜0.15 wt. % copper (Cu), and 0.12 wt. % chromium (Cr); 0.10˜0.15 wt. % oxygen (O); 0.006˜0.010 wt. % carbon (C); 0.006˜0.010 wt. % silicon (Si); 0.0005˜0.0020 wt. % sulfur (S); and the balance zirconium (Zr). The zirconium alloy manufactured with the composition in accordance with the present invention has an excellent creep resistance compared to a conventional Zircaloy-4, and may effectively be used as a nuclear cladding tube, supporting lattice and inner structures of reactor core in the nuclear power plant utilizing light or heavy water reactor.

Abstract: A NOR flash memory device is capable of shortening a program time. Included is a cell array segmented into a plurality of banks, a data input buffer to receive and store data composed of units of words, the number of units corresponding to the number of banks, and a program driver to apply a program voltage contemporaneously to the banks. According to the present invention, a plurality of program data composed of word units is programmed at the same time, so that the time for programming the whole memory cell array can be shortened.

Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract: Memory cells in a memory cell array are erased using an erase operation followed by a post-program operation. In the erase operation, an erase voltage is applied to a plurality of memory cells of the memory cell array. In the post program operation, a program voltage is simultaneously applied to at least two word lines coupled to ones of the plurality of erased memory cells of the memory cell array. Related devices are also discussed.

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device comprises a plurality of memory cells that are programmed by supplying first and second program voltages thereto. In cases where the second program voltage rises above a predetermined detection voltage, the first program voltage is prevented from being supplied to the memory cell until the second program voltage falls below the detection voltage.