Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract: A method for building a software project, the method including the steps of receiving a makefile for building one software project, generating an object list of the received makefile, selecting one build target from the generated object list according to a preset order, sequentially compiling the child modules included in the build target when the selected build target includes child modules, updating a library file of an ancestor module having an inheritance relation with each of the compiled child modules, determining if all the build targets in the object list have been compiled; and generating a new execution file by using results obtained by compiling all the build targets when all the build targets have been compiled.

Abstract: An electroluminescence display device including a thin film transistor layer formed on a substrate, at least one insulating layer, and a pixel layer that includes a first electrode layer, a second electrode layer, and an intermediate layer interposed between the first electrode layer and the second electrode layer and having at least an emitting layer. The pixel layer further includes a reflection layer that is disposed under the first electrode layer and that extends to a via hole formed in the insulating layer, and an auxiliary conductive layer is disposed under the reflection layer. The auxiliary conductive layer extends to the via hole, and the first electrode layer contacts at least a portion of the auxiliary conductive layer.

Abstract: A non-volatile semiconductor memory device comprises a plurality of memory sectors arranged in different memory banks having different bulk regions. The memory cells can be erased using a first mode erase operation, which determines different erase pass voltages for the respective memory sectors by successively increasing a bank voltage applied to each sector until the number of failed cells in each sector falls below a first failed cell threshold value, and a second mode erase operation, which applies the different erase pass voltages to the respective memory sectors for successively increasing periods of time until the number of failed cells in each sector falls below a second failed cell threshold value.

Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract: Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.

Abstract: Data verification methods and/or nonvolatile memory devices are provided that concurrently detect data for a selected memory cell of the nonvolatile memory device and verify a programmed or erase state of previously detected data of a different memory cell of the nonvolatile memory device. Concurrently detecting data and verifying a programmed or erase state may be provided by a sense amplifier configured to sense data from a memory cell of the nonvolatile memory device, a latch configured to store the data sensed by the sense amplifier, an I/O buffer configured to store the data stored in the latch and a program/erase verifier circuit configured to control the sense amplifier, latch and I/O buffer to provided previously sensed data for a first memory cell to the program erase/verifier circuit for verification while the sense amplifier is sensing data for a second memory cell.

Abstract: In a drive IC and a display device having the same, the drive IC includes a plurality of bumps disposed on a lower surface of the drive IC and aligned in a plurality of rows along an edge of the drive IC. The bumps aligned in different rows from each other are juxtaposed in a direction perpendicular to a direction in which the bumps are aligned. Accordingly, when the drive IC is mounted on a display panel using an anisotropic conductive film, the anisotropic conductive film may be smoothly flowed through a space defined by the bumps of the drive IC, thereby improving electric properties of the drive IC and display device.

Abstract: A light guide plate includes a main body having opposing side faces, and front and rear faces connected to the opposing side faces, the front face being adapted to output light incident on at least one of the side faces, a plurality of front prisms disposed at the front face of the main body, and a plurality of dot prisms disposed in an array at the rear face of the main body, the dot prisms being spaced apart from each other, each of the dot prisms including prism parts, sizes of the dot prisms increasing as a distance from the at least one side face increases.

Abstract: A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.

Abstract: A nonvolatile memory device and method of programming the device are disclosed. The nonvolatile memory device is adapted to interrupt or resume a programming operation for a memory cell of the device in response to variation in a programming voltage being supplied to the memory cell. The programming operation is typically interrupted or resumed in response to signals generated by a program controller and/or a detector monitoring the programming voltage.

Abstract: A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage is less than the detection voltage, a second pump becomes active.

Abstract: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of a substrate on source/drain electrode of a thin film transistor having a semiconductor layer, a gate, source/drain areas and the source/drain electrodes, and a blanket etching process is performed to the organic planarization layer to planarize the inorganic layer. After forming a photoresist pattern on the inorganic layer, an etching process is performed to form a hole coupling a pixel electrode with one of the source/drain electrodes. According to the manufacturing method, the hole may be formed using one mask, thereby simplifying a manufacturing process, and improving an adhesion with the pixel electrode by the inorganic layer formed above.

Abstract: In a drive IC and a display device having the same, the drive IC includes a plurality of bumps disposed on a lower surface of the drive IC and aligned in a plurality of rows along an edge of the drive IC. The bumps aligned in different rows from each other are juxtaposed in a direction perpendicular to a direction in which the bumps are aligned. Accordingly, when the drive IC is mounted on a display panel using an anisotropic conductive film, the anisotropic conductive film may be smoothly flowed through a space defined by the bumps of the drive IC, thereby improving electric properties of the drive IC and display device.

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by a first pump. However, where the bulk voltage exceeds a predetermined detection voltage, a second pump is further activated in order to lower the bulk voltage.

Abstract: A high voltage cable for a vehicle is disclosed which comprises a braid body portion; a shield body portion; and a holder portion. In preferred systems, the structure of a shield body portion with a braid portion of the high voltage cable for the vehicle being engaged and a holder portion can be changed, and the shield body portion, the braid portion, and a holder portion are engaged with each other, whereby wear of the braid portion such as arising from vehicle vibration can be minimized or prevented and thereby avoid shorting of the braid portion.

Abstract: A liquid crystal display includes an array pixel including a plurality of pixels arranged in a matrix. The plurality of pixels include a set of pixels including a pair of center pixels adjacent to each other, and a pair of first-color pixels and a pair of second-color pixels obliquely facing each other across the center pixels. Each pixel includes a pixel electrode and a thin film transistor. The liquid crystal display further includes a plurality of gate lines extending in a row direction for transmitting a gate signal to the pixels, and a plurality of data lines extending in a column direction for transmitting data signals to the pixels. The pixels are subject to polarity inversion.

Abstract: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of a substrate on source/drain electrode of a thin film transistor having a semiconductor layer, a gate, source/drain areas and the source/drain electrodes, and a blanket etching process is performed to the organic planarization layer to planarize the inorganic layer. After forming a photoresist pattern on the inorganic layer, an etching process is performed to form a hole coupling a pixel electrode with one of the source/drain electrodes. According to the manufacturing method, the hole may be formed using one mask, thereby simplifying a manufacturing process, and improving an adhesion with the pixel electrode by the inorganic layer formed above.

Abstract: A plasma display device and a method for driving the plasma display device. In a first subfield, a first voltage is alternately applied to the first and second electrodes by applying a first addressing scheme for converting an on-cell to an off-cell for a sustain period. In a second subfield, the off-cell is converted to the light emitting state. Initialization in a reset period is appropriately performed whether a write addressing method or an erase addressing method is used.

Abstract: A pad area and a method of fabricating the same, wherein the pad area is formed on a substrate to contact a chip on glass (COG) or a chip on flexible printed circuit (COF) with the substrate. Changing a lower structure of the pad area increases contact points between conductive balls and an interconnection layer or reduces a step difference between an interconnection layer and a passivation layer to enhance and ensure electrical connection.