Patents by Inventor Yong Jeong

Yong Jeong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050269946
    Abstract: An organic light emitting display device (OLED) and a method of fabricating the same, in which electric field influence between first and second electrodes is reduced in an edge region of a unit pixel. The OLED includes a substrate, and a thin film transistor (TFT) located on the substrate. A passivation layer is located on the TFT over substantially an entire surface of the substrate, and has a via hole for exposing source or drain electrode, and a groove. A first electrode on the passivation layer is in electrical contact with the exposed source or drain electrode through the via hole, and has an edge located in the groove. A pixel defining layer is located on the first electrode and has an opening for exposing a predetermined portion of the first electrode. An organic layer is in contact with the predetermined portion, and a second electrode is formed on the organic layer.
    Type: Application
    Filed: May 18, 2005
    Publication date: December 8, 2005
    Inventors: Chang-Yong Jeong, Tae-Wook Kang, Chang-Soo Kim
  • Publication number: 20050263761
    Abstract: A TFT having a dual buffer structure, a method of fabricating the same, and a flat panel display having the TFT, and a method of fabricating the same are provided. The TFT includes a first buffer layer formed of an amorphous silicon layer on a substrate, a second buffer layer formed on the first buffer layer. The TFT also includes a semiconductor layer formed on the second buffer layer and a gate electrode formed on the semiconductor layer. The dual buffer structure provides better barrier to impurities diffusing from the substrate, and also acts as a black matrix to reduce unwanted reflections and is a source of hydrogen to passivate other layers.
    Type: Application
    Filed: May 9, 2005
    Publication date: December 1, 2005
    Inventors: Chang-Soo Kim, Tae-Wook Kang, Chang-Yong Jeong, Jae-Young Oh, Sang-Il Park, Seong-Moh Seo
  • Publication number: 20050266240
    Abstract: Provided are the high tensile nonmagnetic stainless steel wire for an low loss overhead electric conductor, the low loss overhead electric conductor using the high tensile nonmagnetic stainless steel wire as its core, and a manufacturing method of them respectively. The high tensile nonmagnetic stainless steel wire reduces a core loss and eddy current loss and minimizes effective electric resistance of the conductor by using the nonmagnetic stainless steel wire, that is a non-magnetic material, rather than a high carbon steel wire, that is a strong magnetic material. In addition, an overall power transmission loss is minimized by strengthening the tensile strength of and reducing a sectional area of the steel wire, making an aluminium-welded layer thicker, and increasing the sectional area of an aluminium conductor.
    Type: Application
    Filed: May 25, 2004
    Publication date: December 1, 2005
    Inventors: Byung Kim, Shang Kim, Byung Woo, Hee Lee, Ju Park, Yong Jeong, Min Lee, Sun Ahn
  • Publication number: 20050258771
    Abstract: Provided is a flat display device having a display region in which more than one thin film transistor and more than one pixel are included. The device includes a driving line that supplies driving power to the display region, and an auxiliary driving line, which is coupled with the driving line, is formed in a different layer from the driving line. The driving line may be an identical layer to the source/drain electrodes of the display region.
    Type: Application
    Filed: April 29, 2005
    Publication date: November 24, 2005
    Inventors: Tae-Wook Kang, Chang-Yong Jeong
  • Publication number: 20050260804
    Abstract: A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile.
    Type: Application
    Filed: May 23, 2005
    Publication date: November 24, 2005
    Inventors: Tae-Wook Kang, Chang-Yong Jeong, Chang-Soo Kim, Chang-Su Seo, Moon-Hee Park
  • Publication number: 20050226049
    Abstract: A NOR flash memory device is capable of shortening a program time. Included is a cell array segmented into a plurality of banks, a data input buffer to receive and store data composed of units of words, the number of units corresponding to the number of banks, and a program driver to apply a program voltage contemporaneously to the banks. According to the present invention, a plurality of program data composed of word units is programmed at the same time, so that the time for programming the whole memory cell array can be shortened.
    Type: Application
    Filed: September 30, 2004
    Publication date: October 13, 2005
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-Yong Jeong, Heung-Soo Lim
  • Patent number: 6938116
    Abstract: A flash memory management method is provided. According to the method, when a request to write the predetermined data to a page to which data has been written is made, the predetermined data is written to a log block corresponding to a data block containing the page. When a request to write the predetermined data to the page again is received, the predetermined data is written to an empty free page in the log block. Even if the same page is requested to be continuously written to, the management method allows this to be processed in one log block, thereby improving the effectiveness in the use of flash memory resources.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: August 30, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bum-soo Kim, Gui-young Lee, Jong-min Kim, Ji-hyun In, Je-sung Kim, Sam-hyuk Noh, Sang-lyul Min, Dong-hee Lee, Jae-yong Jeong, Yoo-kun Cho, Jong-moo Choi
  • Publication number: 20050162600
    Abstract: A liquid crystal display includes an array pixel including a plurality of pixels arranged in a matrix. The plurality of pixels include a set of pixels including a pair of center pixels adjacent to each other, and a pair of first-color pixels and a pair of second-color pixels obliquely facing each other across the center pixels. Each pixel includes a pixel electrode and a thin film transistor. The liquid crystal display further includes a plurality of gate lines extending in a row direction for transmitting a gate signal to the pixels, and a plurality of data lines extending in a column direction for transmitting data signals to the pixels. The pixels are subject to polarity inversion.
    Type: Application
    Filed: March 24, 2005
    Publication date: July 28, 2005
    Inventors: Soo-Guy Rho, Keun-Kyu Song, Jeong-Ye Choi, Nam-Seok Roh, Cheol-Woo Park, Mun-Pyo Hong, Ho-Yong Jeong
  • Patent number: 6916580
    Abstract: A positive active material for a rechargeable lithium battery is provided. The positive active material comprises a lithiated intercalation compound and a coating layer formed on the lithiated intercalation compound. The coating layer comprises a solid-solution compound and an oxide compound having at least two coating elements, the oxide compound represented by the following Formula 1: MpM?qOr??(1) wherein M and M? are not the same and are each independently at least one element selected from the group consisting of Zr, Al, Na, K, Mg, Ca, Sr, Ni, Co, Ti, Sn, Mn, Cr, Fe, and V; 0<p<1; 0<q<1; and 1<r?2, where r is determined based upon p and q. The solid-solution compound is prepared by reacting the lithiated intercalation compound with the oxide compound. The coating layer has a fracture toughness of at least 3.5 MPam1/2. A method of making the positive active material is also provided.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: July 12, 2005
    Assignee: Samsung SDE Co., Ltd.
    Inventors: Jae-Phil Cho, Byung-Woo Park, Yong-Jeong Kim, Tae-Jun Kim
  • Publication number: 20050122042
    Abstract: An organic electroluminescent display device has an organic light-emitting element formed on a lower insulating substrate, an upper insulating substrate for sealing the organic light-emitting element, and a static electricity preventing member formed on the outer surface of the lower insulating substrate on which the organic light-emitting element is formed.
    Type: Application
    Filed: November 2, 2004
    Publication date: June 9, 2005
    Inventors: Tae-Wook Kang, Chang-Yong Jeong
  • Publication number: 20050110011
    Abstract: A thin film transistor and a method of manufacturing the same are disclosed. More specifically, there is provided a thin film transistor having a thin film transistor and a method of manufacturing the same wherein an inorganic layer and an organic planarization layer are sequentially formed on the surface of a substrate on source/drain electrode of a thin film transistor having a semiconductor layer, a gate, source/drain areas and the source/drain electrodes, and a blanket etching process is performed to the organic planarization layer to planarize the inorganic layer. After forming a photoresist pattern on the inorganic layer, an etching process is performed to form a hole coupling a pixel electrode with one of the source/drain electrodes. According to the manufacturing method, the hole may be formed using one mask, thereby simplifying a manufacturing process, and improving an adhesion with the pixel electrode by the inorganic layer formed above.
    Type: Application
    Filed: November 22, 2004
    Publication date: May 26, 2005
    Inventors: Choong-Youl Im, Tae-wook Kang, Chang-yong Jeong
  • Publication number: 20050100267
    Abstract: Disclosed are an apparatus and method for converting the wavelength of an optical signal using a multi-mode Fabry-Perot laser diode. The apparatus controls polarization of an external pump optical signal to output a TE polarized pump optical signal, and controls polarization of a probe optical signal to output a TM polarized probe optical signal. The apparatus couples the TM polarized probe optical signal and TE polarized pump optical signal irrespective of the polarization of the optical signals. The apparatus finely controls the polarization of the pump optical signal and the polarization of the probe optical signal such that they conform to TE and TM modes of the Fabry-Perot laser diode, respectively.
    Type: Application
    Filed: April 28, 2004
    Publication date: May 12, 2005
    Inventors: Hark Yoo, Hyuek Lee, Yong Jeong, Yong Hyub Won, Min Kang
  • Patent number: 6891754
    Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: May 10, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Yong Jeong, Sung-Soo Lee
  • Patent number: 6888604
    Abstract: A liquid crystal display includes an array pixel including a plurality of pixels arranged in a matrix. The plurality of pixels include a set of pixels including a pair of center pixels adjacent to each other, and a pair of first-color pixels and a pair of second-color pixels obliquely facing each other across the center pixels. Each pixel includes a pixel electrode and a thin film transistor. The liquid crystal display further includes a plurality of gate lines extending in a row direction for transmitting a gate signal to the pixels, and a plurality of data lines extending in a column direction for transmitting data signals to the pixels. The pixels are subject to polarity inversion.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 3, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soo-Guy Rho, Keun-Kyu Song, Jeong-Ye Choi, Nam-Seok Roh, Cheol-Woo Park, Mun-Pyo Hong, Ho-Yong Jeong
  • Publication number: 20050087480
    Abstract: Provided is a wastewater treatment apparatus for removing nitrogen and phosphorus having an anaerobic tank, an anoxic tank, an aerobic tank and a clarifier, wherein the aerobic tank includes has a baffle installed at one side thereof to form a dissolved oxygen reducing zone for reducing the concentration of dissolved oxygen contained in internally recycled wastewater returned from a dissolved oxygen reducing zone while increasing the concentration of dissolved oxygen contained in treated effluent supplied from a part other than the dissolved oxygen reducing zone of the aerobic tank to a clarifier in a subsequent stage. Since organic matter present in wastewater is effectively used, the efficiency of removing nitrogen and phosphorus can be increased and the amounts of oxygen required throughout the treatment process and organic matter required for denitrification can be reduced. Also, synthesis of cells of microorganisms is suppressed. Therefore, the repair and maintenance costs can be reduced.
    Type: Application
    Filed: June 5, 2002
    Publication date: April 28, 2005
    Inventors: Jong-Bok Park, Jae Lee, Yong Jeong, Gyung-Hae Aoh
  • Publication number: 20050078064
    Abstract: The present invention relates to an organic electroluminescent display and a driving method thereof, which divides one frame into a plurality of subframes. Since the present invention divides one frame into several subframes, and drives an organic EL device with the subframes assigned to the upper bits and with the corrected gray data for representing the detailed grays between the basic grays during the subframes assigned to the lower bits, it is possible to represent sufficient number of grays regardless of the unstable luminescence characteristics of an organic EL device.
    Type: Application
    Filed: September 19, 2002
    Publication date: April 14, 2005
    Inventors: Woong-Kyu Min, Cheol-Woo Park, Ho-Yong Jeong
  • Publication number: 20050045887
    Abstract: A thin film transistor and an active matrix flat panel device. By forming a conductive material layer having multiple profiles, critical dimension (CD) bias is reduced and step coverage is enhanced. The thin film transistor includes the conductive material layer formed on an insulating substrate, wherein the conductive material layer is composed of at least one thin film transistor conductive material layer, and an edge portion of the conductive material layer is composed of multiple profiles with multiple edge taper angles.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 3, 2005
    Inventors: Tae-Wook Kang, Chang-Yong Jeong, Choong-Youl Im
  • Publication number: 20050030790
    Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.
    Type: Application
    Filed: August 27, 2004
    Publication date: February 10, 2005
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jae-Yong Jeong, Sung-Soo Lee
  • Publication number: 20040233703
    Abstract: Embodiments of the invention provide a flash memory device having a column predecoder for selecting all column selection transistors during a stress test, and also provide a stress test method for the flash memory device. An embodiment's column predecoder includes a buffer unit for inputting all column selection signals, decoder units for decoding an output of the buffer unit and column addresses, and level shifters for shifting voltage levels of column selection signals coupled to gates of the column selection transistors in response to an output of the decoder units. Since a ground voltage is applied to a bitline and a high voltage is applied to all column selection signals during the stress test, the stress test time can be shortened.
    Type: Application
    Filed: October 1, 2003
    Publication date: November 25, 2004
    Inventors: Jac-Yong Jeong, Heung-Soo Lim
  • Patent number: 6807098
    Abstract: The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurality of wordlines, and a plurality of registers corresponding to the bitlines. The method involves applying a first voltage to a first one of the bitlines and applying a second voltage to a second one of the bitline, the first bitline being adjacent to the second bitline, the first and second voltages being supplied from the registers; electrically isolating the first and second bitlines from their corresponding registers; charging the first bitline up to a third voltage higher than the first voltage and lower than the second voltage; and applying a fourth voltage to a wordline after cutting off current paths into the first and second bitlines.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: October 19, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Yong Jeong, Sung-Soo Lee