Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract: Memory cells in a memory cell array are erased using an erase operation followed by a post-program operation. In the erase operation, an erase voltage is applied to a plurality of memory cells of the memory cell array. In the post program operation, a program voltage is simultaneously applied to at least two word lines coupled to ones of the plurality of erased memory cells of the memory cell array. Related devices are also discussed.

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device comprises a plurality of memory cells that are programmed by supplying first and second program voltages thereto. In cases where the second program voltage rises above a predetermined detection voltage, the first program voltage is prevented from being supplied to the memory cell until the second program voltage falls below the detection voltage.

Abstract: A method of programming a non-volatile memory device includes activating a first pump to generate a bitline voltage, and after the bulk voltage reaches a target voltage, detecting whether the bitline voltage is less than a detection voltage. When the bitline voltage is less than the detection voltage, a second pump becomes active.

Abstract: Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by a first pump. However, where the bulk voltage exceeds a predetermined detection voltage, a second pump is further activated in order to lower the bulk voltage.

Abstract: Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.

Abstract: A nonvolatile memory device and method of programming the device are disclosed. The nonvolatile memory device is adapted to interrupt or resume a programming operation for a memory cell of the device in response to variation in a programming voltage being supplied to the memory cell. The programming operation is typically interrupted or resumed in response to signals generated by a program controller and/or a detector monitoring the programming voltage.

Abstract: A thin film transistor and an active matrix flat panel device. By forming a conductive material layer having multiple profiles, critical dimension (CD) bias is reduced and step coverage is enhanced. The thin film transistor includes the conductive material layer formed on an insulating substrate, wherein the conductive material layer is composed of at least one thin film transistor conductive material layer, and an edge portion of the conductive material layer is composed of multiple profiles with multiple edge taper angles.

Abstract: A nonvolatile semiconductor memory device has a special test mode and circuitry for counting its own fail bits. During the test mode, test data is stored in the memory, and also in a special expected data buffer. The test data stored in the memory cells are then compared to that stored in the expected data buffer. Where there is no correspondence, fail bits are detected. The lack of correspondence is registered, counted, and output to a data output buffer block.

Abstract: Data verification methods and/or nonvolatile memory devices are provided that concurrently detect data for a selected memory cell of the nonvolatile memory device and verify a programmed or erase state of previously detected data of a different memory cell of the nonvolatile memory device. Concurrently detecting data and verifying a programmed or erase state may be provided by a sense amplifier configured to sense data from a memory cell of the nonvolatile memory device, a latch configured to store the data sensed by the sense amplifier, an I/O buffer configured to store the data stored in the latch and a program/erase verifier circuit configured to control the sense amplifier, latch and I/O buffer to provided previously sensed data for a first memory cell to the program erase/verifier circuit for verification while the sense amplifier is sensing data for a second memory cell.

Abstract: I describe and claim an accelerated bit scanning nonvolatile memory device and method. A nonvolatile memory device comprises a memory cell array including a plurality of memory cells, each memory cell corresponding to program data, a data scanning unit to detect the program data having a first value, and a programming unit to program the memory cells corresponding to the detected portions of the program data responsive to the scanning.

Abstract: A flat panel display includes a sealing substrate formed above a substrate on which a light-emitting device is formed, and a protection plate formed on the sealing substrate to protect the light-emitting device. A plurality of grooves are formed on an inner surface of the protection plate to increase the protection plate's resistance to bending, disperse the force of a load applied to the flat panel display, and decrease the possibility that the light-emitting device formed in the flat panel display will be damaged by the load.

Abstract: An electroluminescent (EL) display device and a method of fabricating the same are provided. The device includes a substrate; a plurality of pixel electrodes disposed on the substrate; a pixel defining layer disposed on the pixel electrodes and having an opening part exposing a predetermined part of each of the pixel electrodes; and at least one barrier layer comprised in and/or on the pixel defining layer. In this device, the pixel defining layer includes at least one barrier layer in order to reduce the amount of outgas from the pixel defining layer and prevent degradation of an emission portion due to the outgas. Also, the pixel defining layer is formed to a sufficiently small thickness to facilitate a subsequent process using a laser induced thermal imaging (LITI) process.

Abstract: Provided is an active matrix electroluminescent display apparatus in which a short circuit between a power line and data line in adjacent sub-pixels can be substantially prevented. The active matrix electroluminescent display apparatus includes: a power line; a first transistor positioned on a side of the power line and connected to the power line; a second transistor positioned on the other side of the power line and connected to the power line; and electroluminescent devices respectively connected to the first transistor and the second transistor.

Abstract: A flash memory device includes a memory cell array arranged in rows and columns; a pad configured to be supplied with a high voltage from the exterior during a stress test operation; a column decoder configured to select a part of the columns in response to column selection signals; and a column predecoder configured to generate the column selection signals in response to an all column selection signal and a column address. The column predecoder simultaneously drives the column selection signals with the high voltage from the pad when the all column selection signal is activated during the stress test operation.

Abstract: A data processor receives sets of input image data having respective input grays and outputs sets of output image data having respective output grays. Each set of output image data corresponds to one of the plurality of sets of input image data and have more image data than each set of the input image data. A data driver supplies the pixels with data voltages corresponding to the output image data supplied from the data processor. A set of output grays corresponding to a set of input grays are selected from sets of grays, each set of grays giving an average front transmittance substantially equal to an average front transmittance of the set of input grays. The sets of output grays generate the closest average lateral gamma curve generated by the sets of grays relative to an average front gamma curve generated by the input grays.

Abstract: A nonvolatile memory device includes a memory cell array, a data scanning unit, and a program unit. The memory cell array includes a plurality of memory cells, where each of the memory cells is programmable to store data have a first logic value or a second logic value. The data scanning unit is configured to search among a plurality of data to be programmed in the memory cells to identify data having the second logic value. The program unit is configured to group the identified data having the second logic value, and to program at least a portion of the group of identified data at a same time into the memory cells.

Abstract: An electroluminescence display device including a thin film transistor layer formed on a substrate, at least one insulating layer, and a pixel layer that includes a first electrode layer, a second electrode layer, and an intermediate layer interposed between the first electrode layer and the second electrode layer and having at least an emitting layer. The pixel layer further includes a reflection layer that is disposed under the first electrode layer and that extends to a via hole formed in the insulating layer, and an auxiliary conductive layer is disposed under the reflection layer. The auxiliary conductive layer extends to the via hole, and the first electrode layer contacts at least a portion of the auxiliary conductive layer.

Abstract: A flat panel display includes a sealing substrate formed above a substrate on which a light-emitting device is formed, and a protection plate formed on the sealing substrate to protect the light-emitting device. A plurality of grooves are formed on an inner surface of the protection plate to increase the protection plate's resistance to bending, disperse the force of a load applied to the flat panel display, and decrease the possibility that the light-emitting device formed in the flat panel display will be damaged by the load.

Abstract: An organic light emitting display and method of fabricating the same are provided. The organic light emitting display includes: a TFT disposed on a substrate and having a gate electrode and source and drain electrodes; a pixel electrode formed on a planarization layer having a via contact hole on the substrate, connected to one of the source and drain electrodes through the via contact hole, and having an etching surface extending to the planarization layer; a pixel defining layer pattern for defining an emission region formed on the entire surface; an organic layer formed on an emission region of the pixel electrode, and having at least an emission layer; and an opposite electrode formed on the entire surface, thereby preventing the organic layer from being separated from an edge of the pixel electrode and a short circuit from occurring between the pixel electrode and the opposite electrode to improve device characteristics and reliability.