Abstract: A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units.

Abstract: A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal.

Abstract: A method for providing a broadcasting service containing contents includes: generating contents representations metadata for describing possible representations of the contents; and outputting the contents representations metadata, wherein the contents representations metadata includes one or more contents representations description elements which describe a metadata tool defined by a standard specification.

Abstract: A video processing method for a three-dimensional (3D) display is based on a multi-cue process. The method may include acquiring a cut boundary of a shot by performing a shot boundary detection with respect to each frame of an input video, computing a texture saliency with respect to each pixel of the input video, computing a motion saliency with respect to each pixel of the input video, computing an object saliency with respect to each pixel of the input video based on the acquired cut boundary of the shot, acquiring a universal saliency with respect to each pixel of the input video by combining the texture saliency, the motion saliency, and the object saliency, and smoothening the universal saliency of each pixel using a space-time technology.

Abstract: A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.

Abstract: A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.

Abstract: Provided is a three-dimensional (3D) image generating system and method accommodating multi-view imaging. The 3D image generating system and method may generate corrected depth maps respectively corresponding to color images by merging disparity information associated with a disparity between color images and depth maps generated respectively from depth images.

Abstract: A control method of a dryer is disclosed. A control method of a dryer including a heat pump having a inverter compressor includes determining a driving condition of the dryer; and adjusting at least one of an electric power supplied to the inverter compressor and a driving velocity of the compressor based on the driving condition.

Abstract: A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference dock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.

Abstract: A method, system, and medium of providing various types of broadcast services such as a record, a summary, a navigation and a real-time event service with respect to a broadcast content, utilizing a home server, according to a user's request. A broadcast service providing method includes: storing broadcast summary data, navigation data and real-time event data which is generated by analyzing received broadcast data according to a broadcast record request from a user's portable device, in a database; and providing the user's portable device with a streaming service with respect to the stored broadcast summary data, the navigation data and the real-time event data, according to a summary selection request from the user's portable device.

Abstract: A clock signal duty correction circuit includes: a first transition timing control unit configured to generate a first control signal for controlling a rising timing of a duty correction clock signal by using a clock signal; a second transition timing control unit configured to generate a second control signal for varying a falling timing of the duty correction clock signal by using the clock signal according to a code signal; and a differential buffer unit configured to generate the duty correction clock signal, whose rising time or falling time is adjusted, in response to the first control signal and the second control signal.

Abstract: A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a clock signal and generate an internal clock signal; a plurality of data reception units configured to receive parallel data in accordance with the internal clock signal and generate internal data; and a phase control unit configured to control the phase of the internal clock signal to track the tracking clock signal and to compensate for a variation in the phase of the internal clock signal while the data is received.

Abstract: An apparatus and a method for touch input in a portable terminal, more specifically, an apparatus and a method for determining a pop-up menu set in a particular menu using a short touch. The apparatus preferably includes a controller for detecting a menu touch input for executing a function; and a pop-up menu guide unit for determining whether or not a pop-up menu is set in the menu detected by the controller and processing information to be output regarding whether or the pop-up menu is set, according to the determination.

Abstract: Provided are a gas storage structure and a gas storage apparatus including the gas storage structure. The gas storage structure includes a gas storage part including an opening thereon and an entrance control part disposed on the opening and including a gate.

Abstract: A wireless audio delivery system and method are disclosed for distributing an audio signal to a plurality of headsets through short range wireless communication channels. An audio delivery method for a short range wireless communication network including a master device and a plurality of slave devices includes selecting, at the master device, one of the slave devices as a primary slave device, assigning a master control to the primary slave device, establishing a communication channel between the master and the slave devices and delivering audio data to the slave devices through the communication channel.

Abstract: A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.

Abstract: A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock.

Abstract: An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.

Abstract: A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.

Abstract: A voltage adjustment circuit of a semiconductor memory apparatus includes a control voltage generating unit configured to distribute an external voltage for selectively outputting a plurality of distribution voltages as a control voltage in response to a control signal, the plurality of the distribution voltages each have different voltage levels, a comparing unit configured to include a voltage supply unit configured to control an external voltage supplied to a first node and a second node if a level of an output voltage is higher than a level of a reference voltage in response to a level of the control voltage, and a detection signal generating unit configured to drop potential levels of the first and second nodes according to the levels of the output voltage and the reference voltage, and to output the potential level of the second node as a detection signal, and a voltage generating unit configured to drive the external voltage according to a potential level of the detection signal and to output the exter