Abstract: A resistive memory device includes a memory cell array including a plurality vertically stacked layers having one layer designated as an interference-free layer and another layer designated as an access prohibited layer, wherein the interference-free layer and the access prohibited layer share a connection with at least one signal line and access operations directed to memory cells the access prohibited layer are prohibited.

Abstract: Provided are a resistive memory device and a method of the resistive memory device. The method of operating the resistive memory device includes performing a pre-read operation on memory cells in response to a write command; performing an erase operation on one or more first memory cells on which a reset write operation is to be performed, determined based on a result of comparing pre-read data from the pre-read operation with write data; and performing set-direction programming on at least some memory cells from among the erased one or more first memory cells and on one or more second memory cells on which a set write operation is to be performed.

Abstract: An operating method for a resistive memory device includes; applying a bias control voltage to a memory cell array of the resistive memory device, measuring leakage current that occurs in the memory cell array in response to the applied bias control voltage to generate a measuring result, generating a control signal based on the measuring result, and adjusting a level of the bias control voltage in response to the control signal.

Abstract: A method of writing data in a resistive memory device having a memory cell array divided into first and second tiles includes; performing a first simultaneous write operation by performing a set write operation performed on resistive memory cells of the first tile while simultaneously performing a reset write operation on resistive memory cells of the second tile in response to the write command, and performing a second simultaneous write operation by performing a reset write operation on resistive memory cells of the first tile while simultaneously performing a set write operation on resistive memory cells of the second tile in response to the write command.

Abstract: In operating a resistive memory device including a number of memory cells, a write pulse is applied to each of the plurality of memory cells such that each of the memory cells has a target resistance state between a first reference resistance and a second reference resistance higher than the first reference resistance. The resistance of each of the memory cells is read by applying a verify pulse to each of the plurality of memory cells. A verify write current pulse is applied to each of the memory cells that has resistance higher than the second reference resistance, and a verify write voltage pulse is applied to each of the memory cells that has resistance lower than the first reference resistance.

Abstract: Provided are a resistive memory device and an operating method for the resistive memory device. The operating method includes detecting a write cycle, determining whether or not to perform a recovery operation by comparing the detected write cycle with a first reference value, and upon determining to perform the recovery operation, performing the recovery operation on target memory cells of the memory cell array.

Abstract: A method of reading a memory device that includes a memory cell that stores data of at least two bits includes determining whether a cell resistance level is no greater than a threshold resistance level. If the cell resistance level is smaller than or equal to the threshold resistance level, then the data is read based on a first factor that is inversely proportional to the cell resistance level. If the cell resistance level is greater than the threshold resistance level, then the data is read based on a second factor that is proportional to the cell resistance level.

Abstract: A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.

Abstract: A resistive memory device including multiple resistive memory cells arranged in regions where first signal lines and second signal lines cross each other, and a method of operating the resistive memory device, are provided. The method includes applying a first voltage to a first line, from among unselected first signal lines connected to unselected memory cells, that is not adjacent to a selected first signal line connected to a selected memory cell from among the multiple memory cells; applying a second voltage that is lower than the first voltage to a second line, from among the unselected first signal lines, that is adjacent to the selected first signal line; floating the unselected first signal lines; and applying a third voltage that is higher than the first voltage to the selected first signal line.

Abstract: A method of programming memory cells of a resistive memory device includes; applying a first current pulse to each of the plurality of memory cells; applying a second current pulse that increases by a first difference compared to the first current pulse to each of the plurality of memory cells to which the first current pulse is applied; and applying a third current pulse that increases by a second difference compared to the second current pulse to each of the plurality of memory cells to which the second current pulse is applied, wherein the first through third current pulses non-linearly increase, and the second difference is greater than the first difference.

Abstract: Methods of operating a memory device include; applying a first set write voltage to a selected first signal line connected to a selected memory cell, applying a first inhibition voltage to non-selected first signal lines connected to non-selected memory cells, and controlling a first voltage of a selected second signal line connected to the selected memory cell to be less than the first set write voltage, and a difference between the first inhibition voltage and the first voltage is less than a threshold voltage of the selection element.

Abstract: A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.

Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.

Abstract: A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Abstract: An open fare payment method for a fare payment terminal device which performs a fare transaction process, includes: receiving fare transaction information from a fare media, determining a network state between a device and a central system, and receiving an authorization result of the fare transaction information from the central system according to the network state such that the device authorizes the fare transaction information or authorizes the fare transaction information by itself independently based on authorization reference information in the fare payment terminal device.

Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.

Abstract: A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.

Abstract: A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.