Patents by Inventor Yong-Kyu Lee

Yong-Kyu Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9082865
    Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: July 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tea-Kwang Yu, Kwang-Tae Kim, Yong-Tae Kim, Bo-Young Seo, Yong-Kyu Lee, Hee-Seog Jeon
  • Publication number: 20150179244
    Abstract: A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.
    Type: Application
    Filed: October 8, 2014
    Publication date: June 25, 2015
    Inventors: Bo-Young Seo, Yong-Kyu Lee, Choong-Jae Lee, Hee-Seog Jeon
  • Publication number: 20150155024
    Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.
    Type: Application
    Filed: July 31, 2014
    Publication date: June 4, 2015
    Inventors: Bo-Young SEO, Yong-Kyu Lee, Choong-Jae Lee, Kee-Moon Chun, Hee-Seog Jeon
  • Publication number: 20150073882
    Abstract: An open fare payment method for a fare payment terminal device which performs a fare transaction process, includes: receiving fare transaction information from a fare media, determining a network state between a device and a central system, and receiving an authorization result of the fare transaction information from the central system according to the network state such that the device authorizes the fare transaction information or authorizes the fare transaction information by itself independently based on authorization reference information in the fare payment terminal device.
    Type: Application
    Filed: May 27, 2014
    Publication date: March 12, 2015
    Applicant: LG CNS CO., LTD.
    Inventors: Seung A LIM, Yong Kyu LEE
  • Patent number: 8921816
    Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: December 30, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Bo-Young Seo, Byung-Suo Shim, Yong-Kyu Lee, Tea-Kwang Yu, Ji-Hoon Park
  • Patent number: 8913430
    Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Tea-Kwang Yu, Bo-Young Seo
  • Publication number: 20140204650
    Abstract: A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type.
    Type: Application
    Filed: March 12, 2013
    Publication date: July 24, 2014
    Inventors: YONG-KYU LEE, BO-GEUN KIM
  • Publication number: 20140169068
    Abstract: A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers.
    Type: Application
    Filed: November 19, 2013
    Publication date: June 19, 2014
    Inventors: YONG-KYU LEE, BO-GEUN KIM
  • Publication number: 20130308382
    Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.
    Type: Application
    Filed: July 31, 2013
    Publication date: November 21, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Kyu LEE, Tea-Kwang YU, Bo-Young SEO
  • Publication number: 20130242659
    Abstract: A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate.
    Type: Application
    Filed: January 17, 2013
    Publication date: September 19, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Tea-Kwang Yu, Kwang-Tae Kim, Yong-Tae Kim, Bo-Young Seo, Yong-Kyu Lee, Hee-Seog Jeon
  • Patent number: 8526231
    Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: September 3, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Tea-Kwang Yu, Bo-Young Seo
  • Patent number: 8476130
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: July 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tea-Kwang Yu, Byung-Sup Shim, Yong-Kyu Lee, Bo-Young Seo, Yong-Tae Kim
  • Publication number: 20120087189
    Abstract: A non-volatile memory device includes a first sector including a first sector selection transistor and a first plurality of pages connected to the first sector selection transistor, and a second sector including a second sector selection transistor and a second plurality of pages connected to the second sector selection transistor. Each of the first and second plurality of pages includes a memory transistor and a selection transistor, and a number of pages in the first plurality of pages is greater than a number of pages in the second plurality of pages.
    Type: Application
    Filed: July 7, 2011
    Publication date: April 12, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Kyu Lee, Tea-Kwang Yu, Bo-Young Seo
  • Publication number: 20120070949
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.
    Type: Application
    Filed: July 12, 2011
    Publication date: March 22, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tea-Kwang Yu, Byung-Sup Shim, Yong-Kyu Lee, Bo-Young Seo, Yong-Tae Kim
  • Publication number: 20120018797
    Abstract: A nonvolatile memory device includes a device isolation film defining an active region in a semiconductor substrate, a pocket well region formed in an upper portion of the active region and having a first conductivity type, a gate electrode formed on the active region and extending to intersect the active region, a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially disposed between the active region and the gate electrode, a source region and a drain region respectively formed in a first region and a second region of the active region exposed on both sides of the gate electrode, and each having a second conductivity type opposite to the first conductivity type, a pocket well junction region formed in the first region adjacent to the source region and contacting the pocket well region, and having the first conductivity type, and a metal silicide layer formed in the first region and contacting the source region and the pocket well junction region.
    Type: Application
    Filed: June 24, 2011
    Publication date: January 26, 2012
    Inventors: Tea-Kwang YU, Yong-Tae KIM, Byung-Sup SHIM, Yong-Kyu LEE, Bo-Young SEO, Ji-Hoon PARK
  • Publication number: 20120007212
    Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 12, 2012
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Bo-Young SEO, Byung-Suo Shim, Yong-Kyu Lee, Tea-Kwang Yu, Ji-Hoon Park
  • Patent number: 8053342
    Abstract: A mask read-only memory (ROM) device, which can stably output data, includes an on-cell and an off-cell. The on-cell includes an on-cell gate structure on a substrate and an on-cell junction structure within the substrate. The off-cell includes an off-cell gate structure on the substrate and an off-cell junction structure within the substrate. The on-cell gate structure includes an on-cell gate insulating film, an on-cell gate electrode and an on-cell gate spacer. The on-cell junction structure includes first and second on-cell ion implantation regions of a first polarity and third and fourth on-cell ion implantation regions of a second polarity. The off-cell gate structure includes an off-cell gate insulating film, an off-cell gate electrode and an off-cell gate spacer. The off-cell junction structure includes first and second off-cell ion implantation regions of the first polarity and a third off-cell ion implantation region of the second polarity.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Young-Ho Kim, Myung-Jo Chun, Jung-Ho Moon
  • Patent number: 7944753
    Abstract: In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: May 17, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Jung-Ho Moon, Soung-Youb Ha
  • Patent number: 7928492
    Abstract: A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-seog Jeon, Jeong-uk Han, Hyun-khe Yoo, Yong-kyu Lee
  • Publication number: 20110038210
    Abstract: In a method of reading data in an EEPROM cell, a bit line voltage for reading is applied to the EEPROM cell including a memory transistor and a selection transistor. A first voltage is applied to a sense line of the memory transistor. A second voltage greater than the first voltage is applied to a word line of the selection transistor. A current passing through the EEPROM cell is compared with a predetermined reference current to read the data stored in the EEPROM cell. An on-cell current of the EEPROM cell may be increased in an erased state and the data in the cell may be readily discriminated.
    Type: Application
    Filed: October 26, 2010
    Publication date: February 17, 2011
    Inventors: Yong-Kyu Lee, Jeong-Uk Han, Hee-Seog Jeon, Jung-Ho Moon, Soung-Youb Ha