Patents by Inventor Yong Lim

Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONVERTER AND DISPLAY APPARATUS INCLUDING THE SAME
    Publication number: 20200090576
    Abstract: A converter includes a phase locked loop (“PLL”) unit which outputs a first frequency signal having a first frequency during a first period of one frame and to output a second frequency signal modulated to have a frequency corresponding to a pattern of an image signal during a second period other than the first period, a pulse width modulation (“PWM”) signal generator which generates a PWM signal according to the frequency of the frequency signal outputted from the PLL unit, and a voltage generator which outputs a driving voltage obtained by modulating an input voltage in response to the PWM signal to a voltage output terminal.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Inventors: Woon Yong LIM, Sung Soo CHOI, Ki Hyun PYUN
  • RF SENSING APPARATUS OF PLASMA PROCESSING CHAMBER AND PLASMA PROCESSING CHAMBER INCLUDING SAME
    Publication number: 20200072874
    Abstract: An RF sensing apparatus configured for use with a plasma processing chamber includes a penetration unit opened in an up/down direction, a main return path unit surrounding all or a portion of the penetration unit, and a secondary return path unit located between the penetration unit and the main return path unit, spaced apart from the main return path unit, and surrounding all or a portion of the penetration unit. The main return path unit and the secondary return path unit include a path through which a current flows in one of the up/down directions.
    Type: Application
    Filed: January 29, 2019
    Publication date: March 5, 2020
    Inventors: YOUNG DO KIM, SUNG YONG LIM, CHAN SOO KANG, DO HOON KWON, MIN JU KIM, SANG KI NAM, JUNG MO YANG, JONG HUN PI, KYU HEE HAN
  • PHASE SHIFT FULL BRIDGE CONVERTER USING CLAMP CIRCUIT CONNECTED TO THE CENTER-TAP OF THE TRANSFORMER ON THE SECONDARY SIDE
    Publication number: 20200076318
    Abstract: Disclosed are a new phase shift full bridge (PSFB) converter using a clamp circuit connected to a center-tapped clamp circuit and an operating method thereof. The new PSFB converter using a clamp circuit connected to a center-tapped clamp circuit includes a primary-side circuit including a plurality of inductors connected to one end between a first switch and a second switch which are connected in series and to one end between a third switch and a fourth switch which are connected in series and a secondary-side circuit using a voltage applied by the primary-side circuit and including a clamping circuit configured with a first rectifier diode, a second rectifier diode, a third rectifier diode, a fourth rectifier diode, a first clamping diode, a second clamping diode and a capacitor in a center-tapped clamp circuit.
    Type: Application
    Filed: February 25, 2019
    Publication date: March 5, 2020
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Gun Woo Moon, Cheon-Yong Lim
  • Display device and driving method thereof
    Patent number: 10580339
    Abstract: An exemplary embodiment of present disclosure provides a display device including a first horizontal line, a first delay line, a second delay line, a delay value determiner, and a timing controller. The first horizontal line receives a gate pulse signal (CPV) generated by a gate driver. The first delay line is connected to the first horizontal line to transmit a gate pulse signal received at a first horizontal position as a first delay signal. The second delay line is connected to the first horizontal line to transmit a gate pulse signal received at a second horizontal position as a second delay signal. The delay value determiner generates a horizontal delay signal based on the first delay signal and the second delay signal. The timing controller determines generation times of line latch signals applied to a plurality of data lines based on the horizontal delay signal.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Woon Yong Lim, Ki Hyun Pyun
  • Vertical transistor static random access memory cell
    Patent number: 10580779
    Abstract: A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PU1 and PU2) transistors, and first and second pull-down (PD1 and PD2) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PU1 and PU2. A second bottom electrode connects bottom SD regions of PD1 and PD2. A first shared contact connects the top SD region of PU2 to the gate structure of PU1. A second shared contact connects the top SD region of PD1 to the gate structure of PD2. A first top electrode is connected to the top SD regions of PG1, PU1 and the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG2, PU2 and the first shared contact to define a second storage node of the memory cell.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 3, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kwan-Yong Lim, Ryan Ryoung-Han Kim
  • Data driving device and display device including the same
    Patent number: 10580387
    Abstract: Disclosed are a data driving device and a display device including the same. The display device may include: a timing controller configured to include lock fail data in an input signal and transmit the input signal in each preset period; and a source driver configured to recover the lock fail data from the input signal, and reset an internal circuit in response to the recovered lock fail data.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 3, 2020
    Assignee: Silicon Works Co., Ltd.
    Inventors: Hun Yong Lim, Yong Min Kim, Ju Ho Lee
  • Parallax minimization stitching method and apparatus using control points in overlapping region
    Patent number: 10558881
    Abstract: Provided is a parallax minimization stitching method and apparatus using control points in an overlapping region. A parallax minimization stitching method may include defining a plurality of control points in an overlapping region of a first image and a second image received from a plurality of cameras, performing a first geometric correction by applying a homography to the control points, defining a plurality of patches based on the control points, and performing a second geometric correction by mapping the patches.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: February 11, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Ju Cho, Soon-heung Jung, Hyun Cheol Kim, Jeongil Seo, Joo Myoung Seok, Sangwoo Ahn, Seung Jun Yang, Injae Lee, Hee Kyung Lee, Seong Yong Lim
  • VERTICALLY ORIENTED METAL SILICIDE CONTAINING E-FUSE DEVICE
    Publication number: 20200020631
    Abstract: One illustrative integrated circuit product disclosed herein includes a vertically oriented semiconductor (VOS) structure positioned above a semiconductor substrate, a conductive silicide vertically oriented e-fuse positioned along at least a portion of a vertical height of the VOS structure wherein the conductive silicide vertically oriented e-fuse comprises a metal silicide material that extends through at least a portion of an entire lateral width of the VOS structure, and a conductive metal silicide region in the semiconductor substrate that is conductively coupled to the conductive silicide vertically oriented e-fuse.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • SELECTIVE SHIELDING OF AMBIENT LIGHT AT CHIP LEVEL
    Publication number: 20200013908
    Abstract: A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.
    Type: Application
    Filed: July 4, 2018
    Publication date: January 9, 2020
    Inventors: WANBING YI, JUAN BOON TAN, KIOK BOONE ELGIN QUEK, KHEE YONG LIM, CHIM SENG SEET, RAJESH NAIR
  • Method of manufacturing a vertical SRAM with cross-coupled contacts penetrating through common gate structures
    Patent number: 10529724
    Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Manfred Eller, Kwan-Yong Lim
  • Method to fabricate capacitance-matching FET and related device
    Patent number: 10522614
    Abstract: Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yongtian Hou, Khee Yong Lim, Ming-Tsang Tsai, Elgin Kiok Boone Quek
  • Converter and display apparatus including the same
    Patent number: 10522070
    Abstract: A converter includes a phase locked loop (“PLL”) unit which outputs a first frequency signal having a first frequency during a first period of one frame and to output a second frequency signal modulated to have a frequency corresponding to a pattern of an image signal during a second period other than the first period, a pulse width modulation (“PWM”) signal generator which generates a PWM signal according to the frequency of the frequency signal outputted from the PLL unit, and a voltage generator which outputs a driving voltage obtained by modulating an input voltage in response to the PWM signal to a voltage output terminal.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Woon Yong Lim, Sung Soo Choi, Ki Hyun Pyun
  • EXTENDED DRAIN MOSFETS (EDMOS)
    Publication number: 20190393338
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to extended drain MOSFET structures with a dual oxide thickness and methods of manufacture. The structure includes an extended drain metal oxide semiconductor transistor (EDMOS) comprising a gate structure with a dual oxide scheme.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Inventors: Chia Ching YEO, Khee Yong LIM, Kiok Boone Elgin QUEK, Donald R. DISNEY
  • Vertically oriented metal silicide containing e-fuse device and methods of making same
    Patent number: 10510662
    Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • TASTE MASKING PRODUCT
    Publication number: 20190350850
    Abstract: This invention relates to a chocolate or chocolate substitute composition or product comprising (a) at least compound to be delivered to a subject; (b) a chocolate or chocolate substitute matrix and at least (i) a masking agent or (ii) a firming agent, wherein the composition or product is substantially stable.
    Type: Application
    Filed: November 17, 2017
    Publication date: November 21, 2019
    Inventors: Ngoc Minh Nguyen, Lee Yong Lim
  • CHIMERIC ANTIGEN RECEPTOR AND NATURAL KILLER CELLS EXPRESSING SAME
    Publication number: 20190336533
    Abstract: The present invention provides a chimeric antigen receptor and natural killer cells expressing the same, and particularly, a chimeric antigen receptor (CAR) which includes an intracellular signaling domain including the whole or a portion of an OX40 ligand (CD252), thereby having excellent effects of increasing anticancer activity of immune cells, and immune cells expressing the same.
    Type: Application
    Filed: December 28, 2017
    Publication date: November 7, 2019
    Applicant: Green Cross Lab Cell Corporation
    Inventors: Yu Kyeong HWANG, Sung Yoo CHO, Sung Yong WON, Ho Yong LIM, Jung Hyun HER, Mi Young JUNG, Hyun Ah KIM, Su Hyun GWON, Eun Sol LEE, Han Sol KIM
  • DISPLAY DEVICE AND DRIVER THEREOF
    Publication number: 20190339808
    Abstract: The present disclosure discloses a display device that performs a read operation corresponding to a touch based on a multipoint interface (MPI) protocol. In the display device, a microcontroller and a plurality of drivers share MPI buses and perform the read operation for a touch, and turning on of reception buffers may be efficiently controlled by providing a wake-up signal by a selected driver designated by a read command of the microcontroller to unselected drivers at the time of completion of transmission of touch data.
    Type: Application
    Filed: May 3, 2019
    Publication date: November 7, 2019
    Applicant: SILICON WORKS CO., LTD.
    Inventors: Jong Min PARK, Hun Yong LIM, Hyun Woo JEONG, Young Uk CHANG, Chung Min LEE, Ha Na CHOI
  • Self-aligned single diffusion break isolation with reduction of strain loss
    Patent number: 10468481
    Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Hui Zang, Chun Yu Wong, Kwan-Yong Lim
  • HAIR CARE COMPOSITION COMPRISING NON-VOLATILE HYDROCARBON OILS AND FATTY ESTERS OF BENZOIC ACID
    Publication number: 20190290566
    Abstract: Disclosed is a hair care composition comprising: a cationic surfactant system; a high melting point fatty compound; a fatty ester of benzoic acid; a non-volatile hydrocarbon oil; and an aqueous carrier. The compositions of the present invention provide conditioning benefits, especially dry conditioning benefits, while providing improved clean feel.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Inventors: Mui Siang Soh, Tian Yong Lim
  • HAIR CARE COMPOSITION COMPRISING TRIESTER COMPOUNDS AND FATTY ESTERS OF BENZOIC ACID
    Publication number: 20190290565
    Abstract: Disclosed is a hair care composition comprising: a hair care composition comprising: a cationic surfactant system; a high melting point fatty compound; a fatty ester of benzoic acid; a triester compound; and an aqueous carrier. The compositions of the present invention provide conditioning benefits, especially dry conditioning benefits, while providing improved clean feel.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Inventors: Mui Siang Soh, Tian Yong Lim