Abstract: One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure.

Abstract: Disclosed is a 360 virtual reality (VR) video encoding method. A 360 virtual reality (VR) video encoding method according to the present disclosure includes: dividing the 360 VR video into a plurality of regions based on a division structure of the 360 VR video; generating an region sequence using the divided plurality of regions; generating a bitstream for the generated region sequence; and transmitting the generated bitstream, wherein the region sequence comprises regions having a same position in at least one or more frame included in the 360 VR image.

Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.

Abstract: Provided is a method of manufacturing a grain-refined aluminum-zinc-magnesium-copper alloy sheet, including manufacturing an aluminum alloy sheet from an aluminum-zinc-magnesium-copper alloy melt by twin-roll strip casting, primarily rolling the aluminum alloy sheet manufactured in step 1, cold rolling the aluminum alloy sheet manufactured in step 2, and performing a heat treatment on the aluminum alloy sheet manufactured in step 3, thereby reducing processing time and cost by using twin-roll casting. Since grain refinement and homogenization of the sheet manufactured by the twin-roll casting are maximized by sequentially performing warm rolling, cold rolling, and a heat treatment on the sheet, elongation may be improved.

Abstract: A method for IP traceback is provided comprising receiving a traceback request including the identity of a traceback-deployed autonomous system closest to the destination node in a network routing path, recursively querying a traceback server associated with the traceback-deployed autonomous system to receive the identity of a preceding traceback-deployed autonomous system in the network routing path, and determining the network routing path based on the received identities of traceback-deployed autonomous systems. Additionally, authentication for traceback request is achieved using token delivery, wherein token is fragmented and marking of a packet is performed when a field on the packet matches at least one token fragment.

Abstract: A plasma processing apparatus includes a chamber including a space for processing a substrate, a substrate stage supporting the substrate within the chamber and including a lower electrode, an upper electrode within the chamber facing the lower electrode, a first power supply including a sinusoidal wave power source configured to apply a sinusoidal wave power to the lower electrode to form plasma within the chamber, and a second power supply configured to apply a nonsinusoidal wave power to the upper electrode to generate an electron beam.

Abstract: Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.

Abstract: An apparatus for manufacturing a display device and a method for manufacturing a display device are provided. According to an exemplary embodiment of the present disclosure, an apparatus for manufacturing a display device includes: a pressing pad including a body portion and a vision hole penetrating the body portion; a vision camera above the vision hole; and a suction picker near the pressing pad.

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having an oxide level in a fin array region within a predetermined height of the oxide level of a field region. A first oxide process is performed for controlling a first oxide recess level in a field region adjacent to a fin array region comprising a plurality of fins in a finFET device. The first oxide process comprises depositing an oxide layer over the field region and the fin array region and performing an oxide recess process to bring the oxide layer to the first oxide recess level in the field region. A second oxide process is performed for controlling a second oxide recess level in the fin array region. The second oxide process comprises isolating the fin array region, depositing oxide material, and performing an oxide recess process to bring the oxide level in the fin array region to the second oxide recess level.

Abstract: Provided are a method of manufacturing an aluminum-zinc-based alloy sheet using twin-roll casting and an aluminum-zinc-based alloy sheet manufactured thereby. Specifically, a method of manufacturing an aluminum-zinc-based alloy sheet, including preparing a melt by melting elements corresponding to an aluminum alloy including 0.5 wt % to 10 wt % of zinc, inevitable impurities and aluminum as a balance (step 1); and twin-roll casting by introducing the melt prepared in step 1 between a pair of rotating cooling rolls (step 2), and an aluminum-zinc-based alloy sheet manufactured thereby are provided. The present invention may manufacture an aluminum-zinc-based alloy sheet, in which twin-roll casting is known to be difficult due to a wide solid-liquid coexistence region, by twin-roll casting by using cooling rolls having high thermal conductivity and controlling a reduction force by the rotational speed of the rolls.

Abstract: A method of receiving content in a client is provided. The method may include receiving, from a server, a spatial set identifier (ID) corresponding to a tile group including at least one tile, sending, to the server, a request for first content corresponding to metadata, and receiving, from the server, the first content corresponding to the request.

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

Abstract: A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.

Abstract: Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. A first semiconductor fin is formed that projects from the first device region and a second semiconductor fin is formed that projects from the second device region. A vertical field-effect transistor is formed using the first semiconductor fin, and a saddle fin-type field-effect transistor is formed using the second semiconductor fin. A top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin.

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

Abstract: One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size.

Abstract: A method of receiving content in a client is provided. The method may include receiving, from a server, a spatial set identifier (ID) corresponding to a tile group including at least one tile, sending, to the server, a request for first content corresponding to metadata, and receiving, from the server, the first content corresponding to the request.

Abstract: One illustrative method disclosed includes, among other things, forming a gate around an initial fin structure and above a layer of insulating material, and performing a fin trimming process on an exposed portion of the initial fin structure in the source/drain region so as to produce a reduced-size fin portion positioned above a surface of a layer of insulating material in the source/drain region of the device, wherein the the reduced-size fin portion has a second size that is less than the first size. In this example, the method also includes forming a conformal epi semiconductor material on the reduced-size fin portion and forming a conductive source/drain contact structure that is conductively coupled to and wrapped around the conformal epi semiconductor material.

Abstract: A device and methods for forming the device are disclosed. The method includes providing a substrate prepared with a memory cell region and forming memory cell pairs in the cell region. The memory cell pair comprises of first and second split gate memory cells. Each memory cell includes a first gate serving as an access gate, a second gate adjacent to the first gate, the second gate serving as a storage gate, a first source/drain (S/D) region adjacent to the first gate and a second S/D region adjacent to the second gate. The method also includes forming silicide contacts on the substrate on the gate conductors and first S/D regions and exposed buried common source lines (SLs) in pick-up regions, such that increasing the displacement distance in the wordline and source line (WLSL) region to an extended displacement distance DE avoids shorting between the first offset access gate conductors and adjacent access gate conductors of the rows of memory cell pairs.

Abstract: One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure.