Abstract: A Device which can salvage the waste water from Reverse Osmosis Water Filter up to 100%, in others words, “Zero Waste”, without using electricity and electrical pump, and regardless of whether hot water pipeline and hot water tank are available. It channels the waste water into the cold water pipeline. This Device can be utilized in new Reverse Osmosis Water Filters and existing Reverse Osmosis Water Filter units. This Device consists of two components, a water tank and a special gadget. The special gadget is installed inside the water tank and is not exposed to external view. The water tank can be of various sizes to suit usage requirement. The Device is connected to the outlet of the said waste water outlet, the pipeline Inflow and the outflow to the faucet. The water tank is for receiving and storing the waste water and the special gadget is for salvaging and channelling the waste water to the faucet outlet, when the faucet is turned on, thereby salvaging the waste water.

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

Abstract: At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins.

Abstract: There are provided a device-to-device communication method, a mobile device using the same, and a device-to-device communication control method. The device-to-device communication method according to the invention may include receiving device-to-device communication resource allocation information and transmission characteristics information for device-to-device communication from a base station, and performing direct communication with an opposite terminal using the transmission characteristics information for device-to-device communication and the device-to-device communication resource allocation information, in which the transmission characteristics information includes the number of redundancy versions to be transmitted within at least one consecutive transmission time interval (TTI).

Abstract: A device and methods for forming the device are disclosed. The method includes providing a substrate prepared with a memory cell region and forming memory cell pairs in the cell region. The memory cell pair comprises of first and second split gate memory cells. Each memory cell includes a first gate serving as an access gate, a second gate adjacent to the first gate, the second gate serving as a storage gate, a first source/drain (S/D) region adjacent to the first gate and a second S/D region adjacent to the second gate. The method also includes forming silicide contacts on the substrate on the gate conductors and first S/D regions and exposed buried common source lines (SLs) in pick-up regions, such that increasing the displacement distance in the wordline and source line (WLSL) region to an extended displacement distance DE avoids shorting between the first offset access gate conductors and adjacent access gate conductors of the rows of memory cell pairs.

Abstract: An image correcting unit including: a data converting unit which receives image data, and generates display data by converting respective grayscale values which are included in the image data to high pixel data and low pixel data; and a white pixel detecting unit which detects image data lines which include not less than a first number of white grayscale values from the image data, and outputs a conversion signal when not less than a second number of the detected image data lines are successively arranged, wherein upon receiving the conversion signal from the white pixel detecting unit, the data converting unit converts the white grayscale values which are included in the successively arranged image data lines to first high pixel data and first low pixel data, wherein the first high pixel data and the first low pixel data have a different value from each other.

Abstract: Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. A first semiconductor fin is formed that projects from the first device region and a second semiconductor fin is formed that projects from the second device region. A vertical field-effect transistor is formed using the first semiconductor fin, and a saddle fin-type field-effect transistor is formed using the second semiconductor fin. A top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin.

Abstract: The present invention provides a method and apparatus for deterring pets or other animals from biting or chewing into medication containers. In some embodiments, the invention consists of two or more conductive metal sheets or strips in layers around the side of the container, which are wired to complete a circuit when pressed by the force of an animal's bite or touched by an animal's tongue. In some embodiments, the sheets or strips are spaced or held apart so that a normal human grip would not have sufficient force to complete the circuit. In some embodiments, the device slides onto the medication container with a friction fit, and is removable for use on future containers. In some embodiments, the circuit includes a battery-powered alarm to deter the animal. In other embodiments, the circuit delivers a mild electrical shock to the animal's mouth or tongue through the metal strips or sheets.

Abstract: Disclosed is an apparatus and method for processing information of multiple cameras.

Abstract: A method of forming a thick EG polysilicon over the FG and resulting device are provided. Embodiments include forming a CG on a substrate; forming an STI between a logic region and the CG; forming a polysilicon EG through the CG and CG HM; forming a polysilicon structure over the logic and STI; forming and overfilling with polysilicon a WL trench through the CG and CG HM, between the EG and STI; forming a buffer oxide in the polysilicon structure over the logic region and part of the STI; recessing the buffer oxide and etching back the polysilicon overfill down the CG HM; forming a second buffer oxide over the EG and logic region; recessing the WL polysilicon; removing the first and second buffer oxides; forming a mask with an opening over a center of the WL, the STI, and a majority of the logic region; and removing exposed polysilicon.

Abstract: A transmission method of a mobile station moved in a region of a cell provided by a base station and providing a wireless LAN (local area network). The mobile station receives a plurality of uplink packet flows from a terminal. The mobile station distributes the plurality of uplink packet flows to a plurality of carrier components. Further, the mobile station transmits the plurality of uplink packet flows to the base station through the plurality of carrier components.

Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.

Abstract: Disclosed is a hair conditioning composition comprising: a cationic surfactant; a high melting point fatty compound having a melting point of 25° C. or higher; a material having a refractive index of from about 1.30 to about 1.70; and an aqueous carrier, wherein a composition has a transmittance of at least about 0.5%. The composition is further specified by either: (i) the material is a polyol having at least 3 hydroxyl groups and the polyol is contained at a level of above 30% to about 80% by weight of the composition; or (ii) the cationic surfactant is a salt of a mono-long alkyl amine and an acid. The compositions provides both translucent appearance and conditioning benefits, especially conditioning benefit on wet hair when used as a rinse-off conditioner and/or spreadability on hair.

Abstract: Disclosed are a data driving device and a display device including the same. The display device may include: a timing controller configured to include lock fail data in an input signal and transmit the input signal in each preset period; and a source driver configured to recover the lock fail data from the input signal, and reset an internal circuit in response to the recovered lock fail data.

Abstract: A converter includes a phase locked loop (“PLL”) unit which outputs a first frequency signal having a first frequency during a first period of one frame and to output a second frequency signal modulated to have a frequency corresponding to a pattern of an image signal during a second period other than the first period, a pulse width modulation (“PWM”) signal generator which generates a PWM signal according to the frequency of the frequency signal outputted from the PLL unit, and a voltage generator which outputs a driving voltage obtained by modulating an input voltage in response to the PWM signal to a voltage output terminal.

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.

Abstract: Provided is a method for generating a foreground in a foreground generating apparatus, the method including: extracting a plurality of foregrounds by applying a plurality of background models to an image, the plurality of background models having different ranges of a pixel variance value; generating an intersection foreground based on an intersection region among the extracted plurality of foregrounds; generating a union foreground based on a union region among the extracted plurality of foregrounds; and generating a final foreground based on the intersection foreground and the union foreground.

Abstract: At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal position. A plurality of fins of a transistor is formed. A nitride cap layer on the plurality of fins is formed. An N-type doped region in a first portion of the plurality of fins. A P-type doped region in a second portion of the plurality of fins. A shallow trench isolation (STI) fill process for depositing an STI material on the plurality of fins. A fin reveal process for removing the STI material to a predetermined level. A cap strip process for removing the nitride cap layer for forming a fin reveal position that is self-aligned with the P-type and N-type doped regions.

Abstract: Methods form structures to include a first pair of complementary transistors (having first and second transistors) and a second pair of complementary transistors (having third and fourth transistors). An active area of the first transistor contacts an active area of the second transistor along a first common edge that is straight, and an active area of the third transistor contacts an active area of the fourth transistor along a second common edge that is straight and parallel to the first common edge. The active area of the second transistor has a third edge, opposite the first common edge, that has a non-linear shape, and the active area of the third transistor has a fourth edge, opposite the second common edge, that has the same non-linear shape. The non-linear shape of the third edge faces and is inverted relative to the non-linear shape of the fourth edge.

Abstract: Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary integrated circuit includes a substrate and a dual-bit NVM structure overlying the substrate. The dual-bit NVM structure includes primary, first adjacent and second adjacent fin structures laterally extending in parallel over the substrate. The primary fin structure includes source, channel and drain regions. Each adjacent fin structure includes a program/erase gate. The dual-bit NVM structure further includes a first floating gate located between the channel region of the primary fin structure and the first adjacent fin structure and a second floating gate located between the channel region of the primary fin structure and the second adjacent fin structure. Also, the dual-bit NVM structure includes a control gate adjacent the primary fin structure.