Patents by Inventor Yong Lim

Yong Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Image sensor with stacked SPAD and method for producing the same
    Patent number: 10424568
    Abstract: A method of forming a device including a SPAD detector and a BSI visible light sensor positioned on different planes, the device exhibiting improved resolution and pixel density are provided. Embodiments include a photodiode for detecting visible light; and a SPAD detector for detecting IR radiation, wherein the photodiode and the SPAD detector are on different planes.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: September 24, 2019
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Kian Ming Tan, Khee Yong Lim, Elgin Kiok Boone Quek
  • VERTICAL TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL
    Publication number: 20190267387
    Abstract: A memory cell includes vertical transistors including first and second pass gate (PG) transistors, first and second pull-up (PU1 and PU2) transistors, and first and second pull-down (PD1 and PD2) transistors. A first bottom electrode connects bottom source/drain (SD) regions of PU1 and PU2. A second bottom electrode connects bottom SD regions of PD1 and PD2. A first shared contact connects the top SD region of PU2 to the gate structure of PU1. A second shared contact connects the top SD region of PD1 to the gate structure of PD2. A first top electrode is connected to the top SD regions of PG1, PU1 and the second shared contact to define a first storage node of the memory cell. A second top electrode is connected to the top SD regions of PG2, PU2 and the first shared contact to define a second storage node of the memory cell.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Inventors: Kwan-Yong Lim, Ryan Ryoung-Han Kim
  • METHOD TO FABRICATE CAPACITANCE-MATCHING FET AND RELATED DEVICE
    Publication number: 20190267446
    Abstract: Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Inventors: Yongtian HOU, Khee Yong LIM, Ming-Tsang TSAI, Elgin Kiok Boone QUEK
  • Transistor with source-drain silicide pullback
    Patent number: 10395987
    Abstract: The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Chia Ching Yeo, Kiok Boone Elgin Quek, Khee Yong Lim, Jae Han Cha, Yung Fu Chong
  • Adaptive disturbance rejection using dead zone filter
    Patent number: 10381031
    Abstract: Apparatus and method for disturbance rejection in a control system. In some embodiments, a controller is adapted to position a control object. A disturbance observer generates a disturbance compensation value which is applied to reduce position error resulting from application of mechanical disturbance to the control object. The disturbance observer includes an adaptive filter with at least one dead zone providing a pass-through response with a scalar gain of less than one.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 13, 2019
    Assignees: Seagate Technology LLC, Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Sung-Won Park, Sung-Yong Lim, Jae-Seong Lee, Hyunseok Yang
  • REMOTE MONITORING OF A REGION OF INTEREST
    Publication number: 20190239729
    Abstract: A technology for facilitating remote monitoring of a region of interest. A sensing unit comprising a camera module, sensors and a lighting unit may be provided. The sensors may include one or more time-of-flight (ToF) sensors that measure a depth of the region of interest. The sensing unit may be communicatively coupled to a mobile device. The mobile device may include a non-transitory memory device for storing computer readable program code, and a processor device in communication with the memory device. The processor may be operative with the computer readable program code to perform operations including receiving image data of the region of interest acquired by the camera module and the sensors, determining physical parameters of the region of interest based on the depth and the image data, and presenting the physical parameters and the image data in a report.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 8, 2019
    Inventors: Kwang Yong LIM, Thin Ei San
  • APPARATUS AND METHOD FOR CONTROLLING OBJECT
    Publication number: 20190240578
    Abstract: An apparatus for controlling an object may include a communicator configured to communicate with a first user terminal and a second user terminal, and a processor configured to control a first object corresponding to a first user in a virtual world to be displayed, configured to control the first object to move in the virtual world in response to a movement control of the first user, configured to randomly select at least one candidate object in response to a morphing control of the first user, and configured to change the first object to a second object when the first user selects the second object from the at least one candidate object. Methods for controlling an object are also provided.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 8, 2019
    Inventors: Jung Kyu YE, Geon Yeong KIM, Chang Hoon YI, Joo Seok LEE, Guhyun PARK, Young Suk KIM, Jae Hyun PARK, June Sik YI, Hun Joon HA, Nak Hyun KIM, Ho Sik KIM, Jeong Min SEO, Tae Hoon KOO, Duc Chun KIM, Seoung Hwi JUNG, Byung Eun JIN, Jin Woo LEE, Seok Hyun KIM, Ju Yong LIM, Hyun Ju CHO, Sang Yeop LEE, Min Kwan CHAE, Sang Ho KIM, Hee Seok KANG, Seongkwan LEE, Jeong Pyo HONG, Choong Yeol LEE, Yong Woo PARK, Kyoung Su LEE, Yu Ju KIM, Dong Gook LEE, Hyun Jin KIM, Hyun Jeong LEE, Dong Young CHANG, Jong Min LEE, Jin Woo LEE, Song I HAN, Taek Ki LEE, Eun Ji NAM, Choon Hwa LEE, Young Min KANG, Jung Soo LEE
  • USER EQUIPMENT AND BASE STATION IN CARRIER AGGREGATION SYSTEM, AND CALL ADMISSION CONTROL METHOD FOR USE WITH THE USER EQUIPMENT AND BASE STATION
    Publication number: 20190239263
    Abstract: Disclosed are user equipment and a base station in a carrier aggregation system, and a call admission method thereof. The user equipment includes a plurality of physical layers, and the base station provides multiple component carriers. When messages for connection setup are transmitted and received between the user equipment and base station, the messages include information about what component carriers are selected by the physical layers, information about what component carriers are selectable by the physical layers, and information about calculations for uplink timing alignment, and call admission control and load balancing is performed based on the information included in the messages. Accordingly, in the carrier aggregation system, quicker call admission and load balancing are achieved.
    Type: Application
    Filed: April 14, 2019
    Publication date: August 1, 2019
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Kwang-Ryul JUNG, Soon-Yong LIM, Ae-Soon PARK
  • SELF-ALIGNED SINGLE DIFFUSION BREAK ISOLATION WITH REDUCTION OF STRAIN LOSS
    Publication number: 20190229183
    Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.
    Type: Application
    Filed: January 19, 2018
    Publication date: July 25, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Haiting WANG, Hui ZANG, Chun Yu WONG, Kwan-Yong LIM
  • Method for generating foreground using multiple background models and apparatus thereof
    Patent number: 10346988
    Abstract: Provided is a method for generating a foreground in a foreground generating apparatus, the method including: extracting a plurality of foregrounds by applying a plurality of background models to an image, the plurality of background models having different ranges of a pixel variance value; generating an intersection foreground based on an intersection region among the extracted plurality of foregrounds; generating a union foreground based on a union region among the extracted plurality of foregrounds; and generating a final foreground based on the intersection foreground and the union foreground.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 9, 2019
    Assignees: SAMSUNG SDS CO., LTD., INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Bo Ram Kim, Dae Yong Park, Sun Hee Hwang, Min Song Ki, Kwang Yong Lim, Hye Ran Byun, Seung Jun Lee, Sung Woo Kim, Yoon Seong Kang
  • Apparatus and method for controlling object
    Patent number: 10315112
    Abstract: An apparatus for controlling an object may include a communicator configured to communicate with a first user terminal and a second user terminal, and a processor configured to control a first object corresponding to a first user in a virtual world to be displayed, configured to control the first object to move in the virtual world in response to a movement control of the first user, configured to randomly select at least one candidate object in response to a morphing control of the first user, and configured to change the first object to a second object when the first user selects the second object from the at least one candidate object. Methods for controlling an object are also provided.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: June 11, 2019
    Assignee: Nexon Korea Corporation
    Inventors: Jung Kyu Ye, Geon Yeong Kim, Chang Hoon Yi, Joo Seok Lee, Guhyun Park, Young Suk Kim, Jae Hyun Park, June Sik Yi, Hun Joon Ha, Nak Hyun Kim, Ho Sik Kim, Jeong Min Seo, Tae Hoon Koo, Duc Chun Kim, Seoung Hwi Jung, Byung Eun Jin, Jin Woo Lee, Seok Hyun Kim, Ju Yong Lim, Hyun Ju Cho, Sang Yeop Lee, Min Kwan Chae, Sang Ho Kim, Hee Seok Kang, Seongkwan Lee, Jeong Pyo Hong, Choong Yeol Lee, Yong Woo Park, Kyoung Su Lee, Yu Ju Kim, Dong Gook Lee, Hyun Jin Kim, Hyun Jeong Lee, Dong Young Chang, Jong Min Lee, Jin Woo Lee, Song I Han, Taek Ki Lee, Eun Ji Nam, Choon Hwa Lee, Young Min Kang, Jung Soo Lee
  • Memory device and method of operating the same to prevent occurrence of read fail by adjusting bit line voltage
    Patent number: 10304542
    Abstract: A memory device includes a memory block including a plurality of stacked sub-memory blocks, peripheral circuits configured to perform program, read and erase operations on the memory block or on a block selected from among the sub-memory blocks, and a control logic configured to control the peripheral circuits so that, during a read operation on the memory block, if a block on which a partial erase operation has been performed is not present among the sub-memory blocks, voltages to be used for the read operation are set and so that, if a block on which the partial erase operation has been performed is present among the sub-memory blocks, the voltages to be used for the read operation are varied depending on a position of a sub-memory block that is a target of the read operation.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: May 28, 2019
    Assignee: SK hynix Inc.
    Inventors: Sung Yong Lim, Seung Hwan Baek, Yeon Ji Shin
  • DISPLAY DEVICE
    Publication number: 20190155432
    Abstract: Provided is a display device that transmits and receives data on the basis of a MPI protocol. The display device includes a microcontroller, source drivers, and first and second MPI buses, wherein the microcontroller and the source drivers perform bi-directional communication on the basis of the MPI protocol in which transmission types for occupying the first and second MPI buses are set.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 23, 2019
    Applicant: SILICON WORKS CO., LTD.
    Inventors: Jong Min PARK, Hyun Woo JEONG, Ha Na CHOI, Hun Yong LIM
  • Triple gate technology for 14 nanometer and onwards
    Patent number: 10297672
    Abstract: A method of forming a 14 nm triple gate by adding a MG in the dual gate process and the resulting device are provided. Embodiments include forming an EG region, a MG region and a SG region in a first, second and third portions of a Si substrate, respectively; forming an IL over the EG, MG and SG regions; oxidizing the IL; forming a HK dielectric layer over the IL; performing PDA on the HK dielectric layer; forming a PSA TiN layer over the HK dielectric layer; forming an a-Si cap layer over the PSA TiN layer; forming a photoresist over the a-Si cap layer in the EG and SG regions; removing the a-Si cap layer in the MG region, exposing the PSA TiN layer; stripping the photoresist; and annealing the a-Si cap and PSA TiN layers.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Seong Yeol Mun, Kwan-Yong Lim, Kijik Lee
  • Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device
    Patent number: 10290738
    Abstract: One illustrative method disclosed includes, among other things, forming a gate structure around a fin and above a layer of insulating material, forming a gate spacer adjacent the gate structure and a fin spacer positioned adjacent the fin above the insulating material, the fin spacer leaving an upper surface of the fin exposed, and performing at least one etching process to remove at least a portion of the fin positioned between the fin spacer, the fin having a recessed upper surface that at least partially defines a fin recess positioned between the fin spacer. In this example, the method further includes forming an epi semiconductor material on the fin recess and removing the fin spacer from adjacent the epi semiconductor material while leaving a portion of the gate spacer in position adjacent the gate structure.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Christopher M. Prindle, Kwan-Yong Lim
  • VERTICALLY ORIENTED METAL SILICIDE CONTAINING E-FUSE DEVICE AND METHODS OF MAKING SAME
    Publication number: 20190139892
    Abstract: One illustrative method disclosed herein comprises forming a vertically oriented semiconductor (VOS) structure in a semiconductor substrate and performing a metal silicide formation process to convert at least a portion of the VOS structure into a metal silicide material, thereby forming a conductive silicide vertically oriented e-fuse.
    Type: Application
    Filed: November 7, 2017
    Publication date: May 9, 2019
    Inventors: Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh, Hui Zang
  • TILE-BASED 360 VR VIDEO ENCODING METHOD AND TILE-BASED 360 VR VIDEO DECODING METHOD
    Publication number: 20190141352
    Abstract: Disclosed is a 360 virtual reality (VR) video encoding method. A 360 virtual reality (VR) video encoding method according to the present disclosure includes: dividing the 360 VR video into a plurality of regions based on a division structure of the 360 VR video; generating an region sequence using the divided plurality of regions; generating a bitstream for the generated region sequence; and transmitting the generated bitstream, wherein the region sequence comprises regions having a same position in at least one or more frame included in the 360 VR image.
    Type: Application
    Filed: November 2, 2018
    Publication date: May 9, 2019
    Inventors: Hyun Cheol KIM, Seong Yong LIM, Joo Myoung SEOK
  • Method of manufacturing grain-refined aluminum-zinc-magnesium-copper alloy sheet
    Patent number: 10253403
    Abstract: Provided is a method of manufacturing a grain-refined aluminum-zinc-magnesium-copper alloy sheet, including manufacturing an aluminum alloy sheet from an aluminum-zinc-magnesium-copper alloy melt by twin-roll strip casting, primarily rolling the aluminum alloy sheet manufactured in step 1, cold rolling the aluminum alloy sheet manufactured in step 2, and performing a heat treatment on the aluminum alloy sheet manufactured in step 3, thereby reducing processing time and cost by using twin-roll casting. Since grain refinement and homogenization of the sheet manufactured by the twin-roll casting are maximized by sequentially performing warm rolling, cold rolling, and a heat treatment on the sheet, elongation may be improved.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 9, 2019
    Assignee: Korea Institute of Machinery and Materials
    Inventors: Hyoung-Wook Kim, Yun-Soo Lee, Cha Yong Lim, Jae Hyung Cho
  • CLOUD-BASED FORENSIC IP TRACEBACK
    Publication number: 20190104151
    Abstract: A method for IP traceback is provided comprising receiving a traceback request including the identity of a traceback-deployed autonomous system closest to the destination node in a network routing path, recursively querying a traceback server associated with the traceback-deployed autonomous system to receive the identity of a preceding traceback-deployed autonomous system in the network routing path, and determining the network routing path based on the received identities of traceback-deployed autonomous systems. Additionally, authentication for traceback request is achieved using token delivery, wherein token is fragmented and marking of a packet is performed when a field on the packet matches at least one token fragment.
    Type: Application
    Filed: March 23, 2017
    Publication date: April 4, 2019
    Inventors: Long CHENG, Dinil Mon DIVAKARAN, Wee Yong LIM, Vrizlynn THING
  • PLASMA PROCESSING APPARATUS, PLASMA PROCESSING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
    Publication number: 20190096636
    Abstract: A plasma processing apparatus includes a chamber including a space for processing a substrate, a substrate stage supporting the substrate within the chamber and including a lower electrode, an upper electrode within the chamber facing the lower electrode, a first power supply including a sinusoidal wave power source configured to apply a sinusoidal wave power to the lower electrode to form plasma within the chamber, and a second power supply configured to apply a nonsinusoidal wave power to the upper electrode to generate an electron beam.
    Type: Application
    Filed: March 29, 2018
    Publication date: March 28, 2019
    Inventors: Sang Ki NAM, Sung Yong LIM, Beomjin YOO, Jongwoo SUN, Kyuhee HAN, Kwangyoub HEO, Je-Woo HAN