Patents by Inventor Yong Lu

Yong Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data storage using read-mask-write operation
    Patent number: 7830726
    Abstract: Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: November 9, 2010
    Assignee: Seagate Technology LLC
    Inventors: Henry F. Huang, Hai (Helen) Li, Yong Lu
  • Resistive sense memory array with partial block update capability
    Patent number: 7830700
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.
    Type: Grant
    Filed: November 12, 2008
    Date of Patent: November 9, 2010
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li
  • Compensating for variations in memory cell programmed state distributions
    Patent number: 7830708
    Abstract: Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined.
    Type: Grant
    Filed: April 22, 2009
    Date of Patent: November 9, 2010
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • Variable write and read methods for resistive random access memory
    Patent number: 7826255
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: November 2, 2010
    Assignee: Seagate Technology LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • Polarity dependent switch for resistive sense memory
    Patent number: 7825478
    Abstract: Polarity dependent switches for resistive sense memory are described. A memory unit includes a resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell and a semiconductor transistor in electrical connection with the resistive sense memory cell. The semiconductor transistor includes a gate element formed on a substrate. The semiconductor transistor includes a source contact and a bit contact. The gate element electrically connects the source contact and the bit contact. The resistive sense memory cell electrically connects to the bit contact. The source contact and the bit contact are asymmetrically implanted with dopant material.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: November 2, 2010
    Assignee: Seagate Technology LLC
    Inventors: Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
  • Compensating for Variations in Memory Cell Programmed State Distributions
    Publication number: 20100271875
    Abstract: Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined.
    Type: Application
    Filed: April 22, 2009
    Publication date: October 28, 2010
    Applicant: Seagate Technology LLC
    Inventors: Chulmin Jung, Yong Lu, Harry Hongyue Liu
  • THREE DIMENSIONALLY STACKED NON VOLATILE MEMORY UNITS
    Publication number: 20100265749
    Abstract: A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
    Type: Application
    Filed: April 16, 2009
    Publication date: October 21, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Xuguang Wang, Yong Lu, Hai Li, Hongyue Liu
  • Electric Power Source Arrangement and Method of How to Use It
    Publication number: 20100261085
    Abstract: An electric power source arrangement is described, comprising a fuel cell means (2) having a nominal voltage and a specified voltage-current characteristic, to be connected to a load (1), and comprising a variable DC-DC voltage converter (3), a by-pass branch (11) by-passing the DC-DC voltage converter, a switch (13) alternatively connecting the fuel cell to the DC-DC voltage converter or to the by-pass branch, and a control unit (12) controlling the switch, which control unit (12) comprises a measuring device coupled to the fuel cell means (2) for detecting the operating point thereof and is configured to connect the by-pass branch (11) if the fuel cell means voltage is within a selected range of section (5) of the voltage-current characteristic of the fuel cell means and to disconnect the by-pass branch in the remaining range of sections (4, 6, 7) of said characteristic.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 14, 2010
    Inventors: Zhijun GU, Ke Jin, Yong Lu
  • VARIABLE WRITE AND READ METHODS FOR RESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20100238712
    Abstract: Variable write and read methods for resistance random access memory (RRAM) are disclosed. The methods include initializing a write sequence and verifying the resistance state of the RRAM cell. If a write pulse is needed, then two or more write pulses are applied through the RRAM cell to write the desired data state to the RRAM cell. Each subsequent write pulse has substantially the same or greater write pulse duration. Subsequent write pulses are applied to the RRAM cell until the RRAM cell is in the desired data state or until a predetermined number of write pulses have been applied to the RRAM cell. A read method is also disclosed where subsequent read pulses are applied through the RRAM cell until the read is successful or until a predetermined number of read pulses have been applied to the RRAM cell.
    Type: Application
    Filed: June 4, 2010
    Publication date: September 23, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Haiwen Xi, Hongyue Liu, Xiaobin Wang, Yong Lu, Yiran Chen, Yuankai Zheng, Dimitar V. Dimitrov, Dexin Wang, Hai Li
  • MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS
    Publication number: 20100232211
    Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 16, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Hongyue Liu, Yong Lu, Andrew Carter, Yiran Chen, Hai Li
  • MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE AND MEMORY SYSTEM
    Publication number: 20100218068
    Abstract: Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 26, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yufei LI, Yong LU, Ying WANG, Hao YANG
  • POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY
    Publication number: 20100210095
    Abstract: Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.
    Type: Application
    Filed: May 5, 2010
    Publication date: August 19, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Chulmin Jung, Maroun Georges Khoury, Yong Lu, Young Pil Kim
  • SINGLE LINE MRAM
    Publication number: 20100207219
    Abstract: A magnetic memory device includes a first electrode separated from a second electrode by a magnetic tunnel junction. The first electrode provides a write current path along a length of the first electrode. The magnetic tunnel junction includes a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation. The free magnetic layer is spaced from the first electrode a distance of less than 10 nanometers. A current passing along the write current path generates a magnetic field. The magnetic field switches the free magnetic layer magnetization orientation between a high resistance state magnetization orientation and a low resistance state magnetization orientation.
    Type: Application
    Filed: February 17, 2009
    Publication date: August 19, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Insik Jin, Hongyue Liu, Yong Lu, Xiaobin Wang
  • nvSRAM HAVING VARIABLE MAGNETIC RESISTORS
    Publication number: 20100202191
    Abstract: Non-volatile static random access memory (nvSRAM) that has a six transistor static random access memory (6T SRAM) cell electrically connected to a non-volatile random access memory (nvRAM) cell. The nvRAM cell has first and second variable magnetic resistors and first, second and third transistors.
    Type: Application
    Filed: February 12, 2009
    Publication date: August 12, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yongchul Ahn, Antoine Khoueir, Yong Lu, Hongyue Liu
  • Non-Volatile Memory Cell with Precessional Switching
    Publication number: 20100195380
    Abstract: A method and apparatus for writing data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a selected resistive state is written to a magnetic tunneling structure by applying a succession of indeterminate write pulses thereto until the selected resistive state is verified.
    Type: Application
    Filed: February 3, 2009
    Publication date: August 5, 2010
    Applicant: Seagate Technology LLC
    Inventors: Xiaobin Wang, Yong Lu, Haiwen Xi, Yuankai Zheng, Yiran Chen, Harry Hongyue Liu, Dimitar Dimitrov, Wei Tian, Brian Seungwhan Lee
  • Simultaneously Writing Multiple Addressable Blocks of User Data to a Resistive Sense Memory Cell Array
    Publication number: 20100188883
    Abstract: Method and apparatus are disclosed for storing data to non-volatile resistive sense memory (RSM) memory cells of a semiconductor memory array, including but not limited to resistive random access memory (RRAM) and spin-torque transfer random access memory (STTRAM or STRAM) cells. In accordance with various embodiments, a plurality of addressable data blocks from a host device are stored in a buffer. At least a portion of each of the addressable data blocks are serially transferred to a separate register of a plurality of registers. The transferred portions of said addressable data blocks are thereafter simultaneously transferred from the registers to selected RSM cells of the array.
    Type: Application
    Filed: January 28, 2009
    Publication date: July 29, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
  • TABLE-BASED REFERENCE VOLTAGE CHARACTERIZATION SCHEME
    Publication number: 20100177552
    Abstract: Method and apparatus for reading data from a non-volatile memory cell, such as a modified STRAM cell. In some embodiments, at least a first and second memory cell are read for a plurality of resistance values that are used to select and store a voltage reference for each memory cell.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 15, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Henry F. Huang, Andrew J. Carter, Maroun Khoury, Yong Lu, Yiran Chen
  • BIT SET MODES FOR A RESISTIVE SENSE MEMORY CELL ARRAY
    Publication number: 20100177551
    Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 15, 2010
    Applicant: Seagate Technology LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman
  • BIPOLAR CMOS SELECT DEVICE FOR RESISTIVE SENSE MEMORY
    Publication number: 20100177554
    Abstract: A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.
    Type: Application
    Filed: July 13, 2009
    Publication date: July 15, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yong Lu, Hongyue Liu, Maroun Khoury, Yiran Chen
  • COMPUTER MEMORY DEVICE WITH MULTIPLE INTERFACES
    Publication number: 20100177562
    Abstract: Various embodiments are generally directed to a method and apparatus associated with operating a first memory device with multiple interfaces and a status register. In some embodiments, a first interface is engaged by a host. A memory device that has a plurality of memory cells comprised of at least a magnetic tunneling junction and a spin polarizing magnetic material is connected to a second interface. A status register is maintained by logging at least an error or busy signal during data transfer operations through the first and second interfaces.
    Type: Application
    Filed: January 13, 2009
    Publication date: July 15, 2010
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Yiran Chen, Daniel S. Reed, Yong Lu, Harry Hongyue Liu, Hai Li, Rod V. Bowman