Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Abstract: Embodiments of the invention include methods of protecting sacrificial gates during raised/source drain and replacement metal gate processes. Embodiments include steps of forming sacrificial gates on a semiconductor substrate, protecting the sacrificial gates with gate seals, forming source/drains near the sacrificial gates without substantially growing semiconductor material on the sacrificial gates, removing the gate seals, and replacing the sacrificial gates with metal gates. In some embodiments, the gate seals are made of a high-k material.

Abstract: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.

Abstract: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Abstract: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.

Abstract: The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.

Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.

Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.

Abstract: A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.

Abstract: An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract: An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.

Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.

Abstract: A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.

Abstract: A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.