Patents by Inventor Yong Meng Lee
Yong Meng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100102393Abstract: An integrated circuit that includes a substrate having first and second active regions is disclosed. A first transistor of a first type and a second transistor of a second type are disposed in the first and second active regions respectively. Each transistor includes a gate stack having a metal gate electrode over a gate dielectric layer. First and second gate threshold voltage adjusting (GTVA) layers contacting first and second gate dielectric layer of the first and second transistors are provided. The first GTVA layer tunes a gate threshold voltage of the first transistor. A channel of the second transistor includes dopants to tune the gate threshold voltage of the second transistor.Type: ApplicationFiled: October 29, 2008Publication date: April 29, 2010Applicants: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD., INFINEON TECHNOLOGIES NORTH AMERICA CORP., FREESCALE SEMICONDUCTOR INC.Inventors: James Yong Meng LEE, Jin-Ping HAN, Voon-Yew THEAN
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Publication number: 20100059831Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.Type: ApplicationFiled: November 6, 2009Publication date: March 11, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
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Patent number: 7659174Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.Type: GrantFiled: October 31, 2007Date of Patent: February 9, 2010Assignees: Chartered Semiconductor Manufacturing, Ltd., International Business Machines Corporation (IBM)Inventors: Yong Meng Lee, Haining S. Yang, Victor Chan
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Publication number: 20100009527Abstract: A method for manufacturing an integrated circuit system that includes: providing a substrate; forming a mask layer over the substrate; implanting a first well through an opening in the mask layer into the substrate; and implanting a second well through the mask layer and the opening via a single implant into the substrate.Type: ApplicationFiled: July 14, 2008Publication date: January 14, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Yong Meng Lee, Chung Woh Lai, Huang Liu, Wenzhi Gao, Zhao Lun, Johnny Widodo, Shailendra Mishra, Liang-Choo Hsia
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Patent number: 7615427Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.Type: GrantFiled: June 5, 2006Date of Patent: November 10, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
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Publication number: 20090261448Abstract: A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.Type: ApplicationFiled: April 22, 2008Publication date: October 22, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Shailendra MISHRA, James Yong Meng LEE, Zhao LUN, Wen Zhi GAO, Chung Woh LAI, Huang LIU, Johnny WIDODO, Liang Choo HSIA
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Patent number: 7598572Abstract: An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.Type: GrantFiled: October 25, 2006Date of Patent: October 6, 2009Assignees: International Business Machines Corporation, Samsung Electronic Co., Ltd (Corporation), Chartered Semiconductor Manufacturing Ltd (Corporation)Inventors: Thomas W. Dyer, Sunfei Fang, Ja-Hum Ku, Yong Meng Lee
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Publication number: 20090236663Abstract: A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.Type: ApplicationFiled: March 19, 2008Publication date: September 24, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Lee Wee Teo, Chung Woh Lai, Johnny Widodo, Shyue Seng Tan, Shailendra Mishra, Zhao Lun, Yong Meng Lee, Jeffrey Chee
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Publication number: 20090206408Abstract: A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Johnny WIDODO, Liang Choo HSIA, James Yong Meng LEE, Wen Zhi GAO, Zhao LUN, Huang LIU, Chung Woh LAI, Shailendra MISHRA, Yew Tuck CHOW, Fang CHEN, Shiang Yang ONG
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Publication number: 20090042359Abstract: A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.Type: ApplicationFiled: August 8, 2007Publication date: February 12, 2009Inventors: Richard Lindsay, Yong Meng Lee, Manfred Eller
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Publication number: 20090026549Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.Type: ApplicationFiled: September 30, 2008Publication date: January 29, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Young Way TEH, Yong Meng LEE, Chung Woh LAI, Wenhe LIN, Khee Yong LIM, Wee Leng TAN, John SUDIJONO, Hui Peng KOH, Liang Choo HSIA
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Publication number: 20080315317Abstract: A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor.Type: ApplicationFiled: June 22, 2007Publication date: December 25, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Khee Yong Lim, Young Way Teh, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang-Choo Hsia
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Patent number: 7445978Abstract: An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have an silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.Type: GrantFiled: May 4, 2005Date of Patent: November 4, 2008Assignee: Chartered Semiconductor Manufacturing, LtdInventors: Young Way Teh, Yong Meng Lee, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, John Sudijono, Hui Peng Koh, Liang Choo Hsia
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Publication number: 20080224228Abstract: A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.Type: ApplicationFiled: March 15, 2007Publication date: September 18, 2008Inventors: Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Shailendra Mishra, Johnny Widodo
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Publication number: 20080157223Abstract: A method is provided for manufacturing an integrated circuit having a plurality of MOSFET devices, comprising the steps of: providing a plurality of MOSFET devices each having a first and a second structural parameter associated therewith, wherein a value of one of the first and a second structural parameter of each device is selected to provide a value of a performance parameter of the device substantially equal to a predetermined reference value, the predetermined reference value being the same for each device.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Lee Wee Teo, Yong Meng Lee, Jeffrey Chee, Shyue Seng Tan, Chung Woh Lai, Johnny Widodo, Zhao Lun, Shailendra Mishra
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Patent number: 7393746Abstract: A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed.Type: GrantFiled: October 12, 2006Date of Patent: July 1, 2008Assignees: International Business Machines Corporation, Samsung Electronics Co. Ltd., Infineon Technologies North America Corporation, Chartered Semiconductor Manufacturing, Ltd.Inventors: Thomas W. Dyer, Sunfei Fang, Jiang Yan, Siddhartha Panda, Yong Meng Lee, JunJung Kim
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Publication number: 20080150074Abstract: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.Type: ApplicationFiled: December 21, 2006Publication date: June 26, 2008Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Shailendra Mishra, Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Johnny Widodo
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Publication number: 20080128834Abstract: A method of reducing hot carrier degradation and a semiconductor structure so formed are disclosed. One embodiment of the method includes depositing a silicon nitride layer over a transistor device, ion implanting a species into the silicon nitride layer to drive hydrogen from the silicon nitride layer, and annealing to diffuse the hydrogen into a channel region of the transistor device. The species may be chosen from, for example: germanium (Ge), arsenic (As), xenon (Xe), nitrogen (N), oxygen (O), carbon (C), boron (B), indium (In), argon (Ar), helium (He), and deuterium (De). The ion implantation modulates atoms in the silicon nitride layer such as hydrogen, nitrogen and hydrogen-nitrogen bonds such that hydrogen can be controllably diffused into the channel region.Type: ApplicationFiled: January 16, 2008Publication date: June 5, 2008Applicants: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd. ("CSM")Inventors: Haining Yang, Xiangdong Chen, Yong Meng Lee, Wenhe Lin
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Publication number: 20080102612Abstract: An integrated circuit device having an increased source/drain contact area by a formed silicided polysilicon spacer. The polysilicon sidewall spacer is formed having a height less than seventy percent of said gate conductor height, and having a continuous surface silicide layer over the deep source and drain regions. The contact area is enhanced by the silicided polysilicon spacer.Type: ApplicationFiled: October 25, 2006Publication date: May 1, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, SAMSUNG ELECTRONICS CO., LTD, CHARTERED SEMICONDUCTOR MANUFACTURING LTDInventors: Thomas W. Dyer, Sunfei Fang, Ja-Hum Ku, Yong Meng Lee
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Publication number: 20080090370Abstract: A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed.Type: ApplicationFiled: October 12, 2006Publication date: April 17, 2008Inventors: Thomas W. Dyer, Sunfei Fang, Jiang Yan, Siddhartha Panda, Yong Meng Lee