Patents by Inventor Yong Meng Lee

Yong Meng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080050868
    Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.
    Type: Application
    Filed: October 31, 2007
    Publication date: February 28, 2008
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
    Inventors: Yong Meng Lee, Haining S. Yang, Victor Chan
  • Publication number: 20080048269
    Abstract: An embodiment of the present invention discloses a method of fabricating a structure for an integrated circuit incorporating hybrid orientation technology (HOT) and trench isolation regions. The structure of the integrated circuit comprising: a substrate with a first silicon layer of a first crystalline orientation and a second silicon layer, of a second crystalline orientation different from the first crystalline orientation, disposed on the first silicon layer; a dielectric layer on the substrate; a first silicon active trench region, having first crystalline orientation, extending to the first silicon layer; a second silicon active trench region, having the second crystalline orientation, extending to the second silicon layer, the first silicon active region electrically isolated from the second silicon active region by a portion of the dielectric layer; a first transistor on the first silicon active region; and a second transistor on the second silicon active region.
    Type: Application
    Filed: August 25, 2006
    Publication date: February 28, 2008
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, CHARTERED SEMICONDUCTOR MANUFACTURING LTD. ("CSM")
    Inventors: Xiangdong Chen, Yong Meng Lee
  • Publication number: 20080026523
    Abstract: An example embodiment for a method of fabrication of a semiconductor device comprises the following. We provide a substrate with a first device region and a second device region. We provide a first type FET transistor in the first device region and provide a second type FET transistor in the second device region. We form an etch stop layer over the first and second device regions and forming a first stressor layer over the first device region. The first stressor layer puts a first type stress on the substrate in the first device region. We form a second stressor layer over the second device region. The second stressor layer puts a second type stress on the substrate in the second device region. Another example embodiment is the structure of a dual stress layer device having an etch stop layer.
    Type: Application
    Filed: July 28, 2006
    Publication date: January 31, 2008
    Inventors: Yong Meng Lee, Haining S. Yang, Victor Chan, Eng Hua Lim
  • Patent number: 7309637
    Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: December 18, 2007
    Assignee: Chartered Semiconductor Manufacturing, Ltd
    Inventors: Yong Meng Lee, Haining S. Yang, Victor Chan
  • Publication number: 20070281410
    Abstract: A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 6, 2007
    Inventors: Yong Meng Lee, Young Way Teh, Chung Woh Lai, Wenhe Lin, Khee Yong Lim, Wee Leng Tan, Hui Peng Koh, John Sudijono, Liang Choo Hsia
  • Patent number: 7256084
    Abstract: An example method embodiment forms spacers that create tensile stress on the substrate on both the PFET and NFET regions. We form PFET and NFET gates and form tensile spacers on the PFET and NFET gates. We implant first ions into the tensile PFET spacers to form neutralized stress PFET spacers. The neutralized stress PFET spacers relieve the tensile stress created by the tensile stress spacers on the substrate. This improves device performance.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: August 14, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Khee Yong Lim, Wenhe Lin, Chung Woh Lai, Yong Meng Lee, Liang Choo Hsia, Young Way Teh, John Sudijono, Wee Leng Tan, Hui Peng Koh
  • Publication number: 20070161244
    Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
    Type: Application
    Filed: November 22, 2005
    Publication date: July 12, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian J. Greene, Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim, Young Way Teh
  • Patent number: 7141854
    Abstract: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: November 28, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yong Meng Lee, Da Jin, David Vigar
  • Patent number: 7037791
    Abstract: In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: May 2, 2006
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lay Cheng Choo, James Yong Meng Lee, Lap Chan
  • Publication number: 20060014336
    Abstract: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double-gated transistor.
    Type: Application
    Filed: July 5, 2005
    Publication date: January 19, 2006
    Inventors: Yong Meng Lee, Da Jin, David Vigar
  • Patent number: 6927104
    Abstract: A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 9, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yong Meng Lee, Da Jin, David Vigar
  • Patent number: 6835609
    Abstract: A method of forming a double gated SOI channel transistor comprising the following steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI silicon oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned silicon layer. A dummy layer is formed over the SOI silicon oxide layer and the patterned SOI silicon layer. The dummy layer is patterned to form a damascene opening therein exposing: a portion of the lower SOI silicon oxide layer; and a central portion of the patterned SOI silicon layer to define a source structure and a drain structure. Patterning the exposed lower SOI silicon oxide layer to form a recess. Gate oxide layer portions are formed around the exposed portion of the patterned SOI silicon layer. A planarized layer portion is formed within the final damascene opening. The planarized layer portion including a bottom gate and a top gate.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: December 28, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yong Meng Lee, Da Jin, Mau Lam Lai, David Vigar, Siow Lee Chwa
  • Patent number: 6787404
    Abstract: A method of forming a double-gated transistor comprising the following sequential steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned SOI silicon layer including a source region and a drain region connected by a channel portion. An encasing oxide layer is formed over the patterned SOI silicon layer to form an encased patterned SOI silicon layer. A patterned dummy layer is formed over the encased patterned SOI silicon layer. The patterned dummy layer having an opening, with exposed side walls, exposing: the channel portion of the encased patterned SOI silicon layer; and portions of the upper surface of the SOI oxide layer. Offset spacers are over the exposed side walls of the patterned dummy layer opening.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: September 7, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yong Meng Lee, Da Jin, David Vigar
  • Patent number: 6747314
    Abstract: A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: June 8, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy, Jia Zhen Zheng, Lap Chan, Elgin Quek
  • Patent number: 6709934
    Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: March 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd
    Inventors: James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan
  • Publication number: 20030203580
    Abstract: In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 30, 2003
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lay Cheng Choo, James Yong Meng Lee, Lap Chan
  • Patent number: 6583011
    Abstract: A method to grow layers of gate oxide or gate base materials of different thicknesses for dual gate structures. The process starts with a semiconductor surface in which STI regions have been formed and over the surface of which a layer of gate base material has been grown. A dielectric, such as nitride, is deposited, masked and etched over a first region where thin gate base material must be created thereby exposing the surface of the deposited layer of gate base material in that region. The gate base material is etched to the desired thickness, creating a first thin layer of gate base material. A thick first layer of gate electrode material, poly, is deposited over the dielectric thereby including the surface of the first thin layer of gate base material, and polished down to the surface of the dielectric leaving gate electrode material deposited in the opening above the first thin layer of gate base material.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: June 24, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Li Xia, Gao Feng, Yong Meng Lee
  • Publication number: 20030075758
    Abstract: A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer, to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain.
    Type: Application
    Filed: September 12, 2002
    Publication date: April 24, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan, Elgin Quek
  • Patent number: 6541327
    Abstract: A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: April 1, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Lap Chan, Elgin Quek, Ravi Sundaresan, Yang Pan, James Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng
  • Patent number: 6511884
    Abstract: A method of fabricating an isolated vertical transistor comprising the following steps. A wafer having a first implanted region selected from the group comprising a source region and a drain region is provided. The wafer further includes STI areas on either side of a center transistor area. The wafer is patterned down to the first implanted region to form a vertical pillar within the center transistor area using a patterned hardmask. The vertical pillar having side walls. A pad dielectric layer is formed over the wafer, lining the vertical pillar. A nitride layer is formed over the pad dielectric layer. The structure is patterned and etched through the nitride layer and the pad dielectric layer; and into the wafer within the STI areas to form STI trenches within the wafer. The STI trenches are filled with insulative material to form STIs within STI trenches. The patterned nitride and pad dielectric layers are removed. The patterned hardmask is removed.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: January 28, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Elgin Quek, Ravi Sundaresan, Yang Pan, Yong Meng Lee, Ying Keung Leung, Yelehanka Ramachandramurthy Pradeep, Jia Zhen Zheng, Lap Chan