Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

Abstract: A new method is provided for the creation of ultra-thin gate oxide layers. Under the first embodiment, sacrificial oxide and nitride are deposited, openings are created in the layer of nitride where the ultra-thin layer of gate oxide is to be created. A layer of poly is deposited over the layer of nitride. The layer of polysilicon is polished, leaving the poly deposited inside the openings. The nitride is removed leaving the gate structure in place overlying the grown gate oxide. Under the second embodiment, sacrificial oxide and nitride are deposited followed by the deposition of TEOS oxide. The layers of TEOS, oxide and nitride are patterned creating openings that expose the surface areas of the layer of sacrificial oxide where the ultra-thin layers of gate oxide are to be grown. A thin conformal layer of nitride is deposited over the structure, this thin layer of conformal nitride is etched to form thin spacers on the sidewalls of the openings in the layers of TEOS oxide and nitride.

Abstract: A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode.

Abstract: A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas.

Abstract: A first option is a method of forming an ultra thin buffer oxide layer comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A sacrificial oxide layer is formed over the silicon substrate and the STI regions. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A gate dielectric layer is formed over the silicon substrate. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer. A second option is a method of forming an ultra-thin buffer oxide layer, comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided.

Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.

Abstract: A new method of forming selective salicide structures is described whereby robust salicide structures are formed on exposed logic FET'S, while blocking salicide formation on memory FET's. Thus, yielding logic FET's with robust salicide structures which exhibit low sheet rho lines and contacts, while blocking salicide formation on the sensitive memory FET's which operate at low voltage and have low leakage, shallow junctions. A conformal layer of thick silicon nitride in conjunction with a salicide blockout mask forms robust selective salicide structures. These structures exhibit low leakage and lack leakage problems caused by bridging, silicide ribbons or stringers.

Abstract: A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

Abstract: A new method of forming selective salicide structures is described whereby robust salicide structures are formed on exposed logic FET's, while blocking salicide formation on memory FET's. Thus, yielding logic FET's with robust salicide structures which exhibit low sheet rho lines and contacts, while blocking salicide formation on the sensitive memory FET's which operate at low voltage and have low leakage, shallow junctions. A conformal layer of thick silicon nitride in conjunction with a salicide blockout mask forms robust selective salicide structures. These structures exhibit low leakage and lack leakage problems caused by bridging, silicide ribbons or stringers.

Abstract: A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

Abstract: A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

Abstract: A method for a self aligned TX with elevated source/drain (S/D) regions on an insulated layer (oxide) by forming a trench along side the STI and filling the trench with oxide. STI regions are formed in a substrate. A gate structure is formed. LDD regions are formed adjacent to the gate structure in the substrate. Spacers are formed on the sidewall of the gate structure. We etch S/D trenches between the STI regions and the first spacers. The S/D trenches are filled with a S/D insulating layer. Elevated S/D regions are formed over the S/D insulating layer and the LDD regions. A top isolation layer is formed over the STI regions. The invention builds the raised source/drain (S/D) regions on an insulating layer and reduces junction leakage and hot carrier degradation to gate oxide.

Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.

Abstract: A method for forming a self-aligned, recessed channel, MOSFET device that alleviates the problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A substrate with an active area encompassed by a shallow trench isolation (STI) region is provided. A mask oxide layer is then patterned and etched to expose the substrate and a portion of the STI region. The surface is etched and the mask oxide layer is eroded away while creating a gate recess in the unmasked area. A thin pad oxide layer is then grown overlying the surface followed by a deposition of a thick silicon nitride layer covering the surface and filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown causing the pad oxide layer to thicken. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown causing the pad oxide layer to further thicken.

Abstract: A method for a self aligned TX with elevated source/drain (S/D) regions on an insulated layer (oxide) by forming a trench along side the STI and filling the trench with oxide. STI regions are formed in a substrate. A gate structure is formed. LDD regions are formed adjacent to the gate structure in the substrate. Spacers are formed on the sidewall of the gate structure. We etch S/D trenches between the STI regions and the first spacers. The S/D trenches are filled with a S/D insulating layer. Elevated S/D regions are formed over the S/D insulating layer and the LDD regions. A top isolation layer is formed over the STI regions. The invention builds the raised source/drain (S/D) regions on an insulating layer and reduces junction leakage and hot carrier degradation to gate oxide.

Abstract: A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode.

Abstract: A method for forming a gate dielectric having regions with different dielectric constants. A dummy dielectric layer is formed over a semiconductor structure. The dummy dielectric layer is patterned to form a gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the gate opening. A low-K dielectric layer is formed on the high-K dielectric layer. Spacers are formed on the low-K dielectric layer at the edges of the gate opening. The low-K dielectric layer is removed from the bottom of the gate opening between the spacers. The spacers are removed to form a stepped gate opening. The stepped gate opening has both a high-K dielectric layer and a low-K dielectric layer on the sidewalls and at the edges of the bottom of the gate opening and only a high-k dielectric layer in the center of the bottom of the stepped gate opening. A gate electrode is formed in the stepped gate opening.

Abstract: A method for forming a self-aligned, recessed channel, MOSFET device that alleviates the problems due to short channel and hot carrier effects while reducing inter-electrode capacitance is described. A substrate with an active area encompassed by a shallow trench isolation (STI) region is provided. A mask oxide layer is then patterned and etched to expose the substrate and a portion of the STI region. The surface is etched and the mask oxide layer is eroded away while creating a gate recess in the unmasked area. A thin pad oxide layer is then grown overlying the surface followed by a deposition of a thick silicon nitride layer covering the surface and filling the gate recess. The top surface is planarized exposing the pad oxide layer. An additional oxide layer is grown causing the pad oxide layer to thicken. A portion of the silicon nitride layer is etched away and additional oxide layer is again grown causing the pad oxide layer to further thicken.