Patents by Inventor Yong-Soo Cho

Yong-Soo Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060271611
    Abstract: Provided is a synchronization apparatus and method for a receiver that performs synchronization in a digital domain and detects a transmission signal. The synchronization apparatus includes an Analog-to-Digital (A/D) converter for converting a received signal into a digital signal, a frequency synchronizer for synchronizing a frequency using the digital signal output from the A/D converter, a signal detection unit for detecting a transmission symbol from a signal synchronized by the frequency synchronizer, and a residual phase detector for compensating for a residual phase of the transmission symbol output from the signal detection unit and outputting the resulting transmission symbol. The frequency synchronizer is capable of accurately and efficiently compensating for a frequency offset by minimizing the time delay caused by subcarrier synchronization using an improved CORDIC algorithm.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 30, 2006
    Applicants: SAMSUNG ELECTRONICS CO., LTD., CHUNG-ANG UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
    Inventors: Jong-Han Kim, Kyu-In Lee, Yong-Soo Cho, Jae-Kon Lee, Hwan-Seok Song
  • Publication number: 20060233270
    Abstract: Provided are a method and apparatus for uplink carrier frequency synchronization and antenna weight vector estimation in an Orthogonal Frequency Division Multiple Access System (OFDMA) having a smart antenna.
    Type: Application
    Filed: December 16, 2005
    Publication date: October 19, 2006
    Inventors: Jae-Young Ahn, Yong-Soo Cho, Dong-Han Kim
  • Publication number: 20060138569
    Abstract: A semiconductor device according to a exemplary embodiment of the present invention includes a reverse spacer exposing a part of an epitaxial silicon layer on a silicon substrate, a gate oxide layer on at least the epitaxial silicon layer and a gate polysilicon layer on the gate oxide layer and at least part of the reverse spacer, and source/drain terminals including a first doped (shallow junction) region in the silicon substrate at a position exterior to the exposed epitaxial silicon layer and a second doped (deep junction) region neighboring the first doped region. The semiconductor device can thus have an epitaxial silicon channel of nanometer size, an ultra-shallow junction, and a deep junction.
    Type: Application
    Filed: December 20, 2005
    Publication date: June 29, 2006
    Inventor: Yong-Soo Cho
  • Patent number: 7068593
    Abstract: A frequency synchronization apparatus for an orthogonal frequency division multiplexing (OFDM) communication system includes a radio frequency (RF) receiving module for receiving OFDM signal, an analog/digital (A/D) converter connected to the RF receiving module, the A/D converter converting the OFDM signal into a digital signal, a frequency synchronization module connected to the A/D converter, the frequency synchronization module synchronizing carrier frequency, a Fast Fourier Transformer (FFT) connected to the frequency synchronization module, the FFT performing fast Fourier transformation to symbols from the frequency synchronization module, a channel estimation module connected to the FFT, the channel estimation module estimating channel response, an equalizer connected to the FFT and the channel estimation module, the equalizer equalizing channel, a residual phase tracking module connected to the equalizer, the residual phase tracking module tracking residual phase, a demodulator connected to the residu
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: June 27, 2006
    Assignee: Chung-Ang University Industry Academic Cooperation Foundation
    Inventors: Yong Soo Cho, Kyung Won Park
  • Publication number: 20060114812
    Abstract: In an OFDMA-based cellular system, a frame of a downlink signal includes a common slot and traffic slots. The common slot includes a synchronization preamble and a cell search preamble. The synchronization preamble has a structure for synchronizing time and frequency, and the cell search preamble has a cell search structure. The traffic slot includes pilot symbols provided on the time and frequency axes. A cyclic prefix is used to estimate initial symbol synchronization, and the initial symbol synchronization and the synchronization preamble are used to synchronize the frame. The synchronization frame and the cell search preamble are used to estimate time and frequency synchronization. The cell search preamble is used to search cells. When the initial synchronization is performed, the cyclic prefix is used to track the frequency, the synchronization preamble is used to track symbol synchronization, and the cell search preamble is used to track fine frequency synchronization.
    Type: Application
    Filed: November 29, 2002
    Publication date: June 1, 2006
    Inventors: Kwang-Soon Kim, Kyung-Hi Chang, Yong-Soo Cho, Tae-Gon Kim
  • Publication number: 20060072649
    Abstract: Method for providing frequency-hopping OFDMA using symbols of comb patter, the method including the steps of: a) assigning frequency domain signal X(k) of comb pattern (comb symbol, k is frequency index) to modulated data sequence, the comb symbol comprising predetermined number of sub carriers (sub carrier group) which are placed with predetermined interval in the whole available frequency band; b) getting the comb symbol hopped for the comb symbol to have independent frequency offset; and c) inverse fast fourier transforming the comb symbol to time domain signal x(n) (n is time index) and transmitting the signal.
    Type: Application
    Filed: November 26, 2002
    Publication date: April 6, 2006
    Inventors: Kyung-Hi Chang, Kwang-Soon Kim, Yong-Soo Cho, Suk-Won Ha
  • Patent number: 7022576
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a sidewall layer containing impurities is formed on a part of gate electrode, thereby forming a low concentration source/drain electrode for a lightly doped drain (LDD) structure not by conventional ion implanting process but by out diffusion of impurities contained in the sidewall. Thus, it is made possible to minimizes damages of substrate due to ion implanting process, since the number of process of ion implantation may be naturally minimized through the above mentioned ion implantation process according to the present invention. Also, it is made possible for gate electrode to maintain its size independently, regardless of distance between source electrode and drain electrode, by excluding a role of ion implanting mask which has been performed by gate electrode.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: April 4, 2006
    Assignee: DongbuAnam Semiconductor Inc.
    Inventor: Yong Soo Cho
  • Patent number: 6908823
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a passivation layer is temporarily formed on semiconductor substrate and a process of implanting impurities is conducted by the passivation layer as a protection mask, thereby inducing damages of substrate due to ion implantation processes to be minimized. According to the present invention, implantation of impurities depends on thickness of the passivation layer, so that it is made possible to freely control impurity implantation by controlling thickness of passivation layer. Therefore, it is made possible to control a diffusion range of the lightly doped source/drain electrode.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: June 21, 2005
    Assignee: Dongbuanam Semiconductor Inc.
    Inventor: Yong Soo Cho
  • Patent number: 6862261
    Abstract: Disclosed is a zipper type Very high bit-rate Digital Subscriber Line (VDSL) system which comprises a transmitter including an inverse fast Fourier transformer for performing an inverse fast Fourier transform on input data, and a cyclic extension adder for adding a cyclic extension for each symbol to the data output from the inverse fast Fourier transformer and outputting the data to a transmission channel; and a receiver including a cyclic extension remover for removing the cyclic extension from the data received through the transmission channel, and a fast Fourier transformer for performing a fast Fourier transform on the data output from the cyclic extension remover.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: March 1, 2005
    Assignee: Korea Electronics Technology Institute
    Inventors: Jong-Ho Paik, Young-Hwan You, Jin-Woong Cho, Won-Young Yang, Yong-Soo Cho
  • Publication number: 20040132244
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a passivation layer is temporarily formed on semiconductor substrate and a process of implanting impurities is conducted by the passivation layer as a protection mask, thereby inducing damages of substrate due to ion implantation processes to be minimized.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 8, 2004
    Applicant: Dongbu Electronics Co., Ltd.
    Inventor: Yong Soo Cho
  • Publication number: 20040126976
    Abstract: The present invention relates to a method of manufacturing a semiconductor device. According to the present invention, a sidewall layer containing impurities is formed on a part of gate electrode, thereby forming a low concentration source/drain electrode for a lightly doped drain (LDD) structure not by conventional ion implanting process but by out diffusion of impurities contained in the sidewall. Thus, it is made possible to minimizes damages of substrate due to ion implanting process, since the number of process of ion implantation may be naturally minimized through the above mentioned ion implantation process according to the present invention. Also, it is made possible for gate electrode to maintain its size independently, regardless of distance between source electrode and drain electrode, by excluding a role of ion implanting mask which has been performed by gate electrode.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 1, 2004
    Applicant: Dongbu Electronics Co., Ltd.
    Inventor: Yong Soo Cho
  • Publication number: 20040114506
    Abstract: Disclosed is a transmitting and receiving method for reducing a time-varying channel distortion in an orthogonal frequency division multiplex (OFDM) system. In the present invention, the transmitter defines M sub-channels in one data group, mathematically analyzes a change of channel for each path causing a time-varying channel distortion in a high-speed mobile environment by approximation, calculates a weight value based on the mathematical analysis and assigns the calculated weight value to transmit data of each sub-channel. Subsequently, the receiver combines the signals of these M sub-channels and demodulates the combined signals. Accordingly, the present invention greatly reduces a distortion caused by the time-varying channel to improve a bit error rate and a channel estimation performance.
    Type: Application
    Filed: December 31, 2002
    Publication date: June 17, 2004
    Inventors: Kyung-Hi Chang, Yun-Hee Kim, Yong-Soo Cho, Kyung-Won Park
  • Publication number: 20040081191
    Abstract: In a method for recognizing stations in a home network of an OFDM scheme and a method for establishing a link between stations in a home network having a plurality of stations, a node number is assigned to the each station and subchannels corresponding to each node number are assigned to each station, the starting station constructing tones corresponding to the subchannels assigned to its own node number and the node number of the destination station as single OFDM symbol, and placing the OFDM symbol in a frame for transmission, and stations other than the starting station detecting the tones from the frame, recovering the node number using indices of the subchannels obtained from the tones and recognizing the starting station and the destination station.
    Type: Application
    Filed: July 18, 2003
    Publication date: April 29, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Oh-Sang Kwon, Yong-soo Cho, Mi-hyun Lee, Sang-gyu Nam
  • Publication number: 20020145971
    Abstract: A frequency synchronization apparatus for an orthogonal frequency division multiplexing (OFDM) communication system includes a radio frequency (RF) receiving module for receiving OFDM signal, an analog/digital (A/D) converter connected to the RF receiving module, the A/D converter converting the OFDM signal into a digital signal, a frequency synchronization module connected to the A/D converter, the frequency synchronization module synchronizing carrier frequency, a Fast Fourier Transformer (FFT) connected to the frequency synchronization module, the FFT performing fast Fourier transformation to symbols from the frequency synchronization module, a channel estimation module connected to the FFT, the channel estimation module estimating channel response, an equalizer connected to the FFT and the channel estimation module, the equalizer equalizing channel, a residual phase tracking module connected to the equalizer, the residual phase tracking module tracking residual phase, a demodulator connected to the residu
    Type: Application
    Filed: November 26, 2001
    Publication date: October 10, 2002
    Inventors: Yong Soo Cho, Kyung Won Park
  • Patent number: 6414936
    Abstract: Disclosed is a method of estimating carrier frequency offset in an OFDM system. The method includes the steps of forming one OFDM symbol which has M repeated identical signal block, being a base sub-block; forming a 2i number of identical ith sub-blocks using an M/2i number of the M number of base sub-blocks as a unit; and estimating an ith carrier frequency offset &egr;i using a correlation between two adjacent ith sub-blocks in the 8i number of the ith sub-blocks.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: July 2, 2002
    Assignee: Korea Electronics Technology Institute
    Inventors: Jin-Woong Cho, Yong-Bae Dhong, Hyoung-Kyu Song, Jong-Ho Paik, Yong-Soo Cho, Hyung-Gi Kim
  • Publication number: 20020064219
    Abstract: Disclosed is a zipper type Very high bit-rate Digital Subscriber Line (VDSL) system which comprises a transmitter including an inverse fast Fourier transformer for performing an inverse fast Fourier transform on input data, and a cyclic extension adder for adding a cyclic extension for each symbol to the data output from the inverse fast Fourier transformer and outputting the data to a transmission channel; and a receiver including a cyclic extension remover for removing the cyclic extension from the data received through the transmission channel, and a fast Fourier transformer for performing a fast Fourier transform on the data output from the cyclic extension remover.
    Type: Application
    Filed: December 1, 2000
    Publication date: May 30, 2002
    Applicant: Korea Electronics Technology Institute
    Inventors: Jong-Ho Paik, Young-Hwan You, Jin-Woong Cho, Won-Young Yang, Yong-Soo Cho
  • Patent number: D467323
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: December 17, 2002
    Inventor: Yong-Soo Cho