Abstract: Disclosed is a display substrate including multiple repetitive units, a repetitive unit includes multiple sub-pixels, a sub-pixel at least includes a pixel drive circuit, a scan signal line, and an auxiliary signal line, the pixel drive circuit includes a first electrode plate and at least one transistor connected with the first electrode plate through a connection electrode; in a direction perpendicular to the display substrate, the display substrate includes a first conductive layer and a second conductive layer, the auxiliary signal line and the first electrode plate are disposed in the first conductive layer, the scan signal line and the connection electrode are disposed in the second conductive layer, an orthographic projection of the scan signal line on a plane of a base substrate is within a range of an orthographic projection of the auxiliary signal line on the plane of the base substrate.

Abstract: Embodiments of the present disclosure provide a display substrate and a preparation method therefor, and a display apparatus. The display substrate includes multiple repetition units (100), wherein a repetition unit includes a display region (110) and a light transmitting region (120). The display region (110) includes multiple sub-pixels, a sub-pixel includes a pixel drive circuit and a light emitting device, the pixel drive circuit includes a first electrode plate (11), and the light emitting device includes a first electrode (61). The display substrate includes multiple conductive layers. The first electrode plate (11), an electrode plate connection electrode (50), and the first electrode (61) are disposed in different conductive layers.

Abstract: Disclosed is a display panel including a base substrate (101), and a gate drive circuit (40), a plurality of clock signal lines, and a plurality of connecting lines (51) that are disposed on the base substrate (101). The plurality of clock signal lines are located on a side of the gate drive circuit (40) along a first direction (X) and are arranged in sequence. Each connecting line (51) is electrically connected with the gate drive circuit (40) and a clock signal line. At least one connecting line (51) includes a load adjusting portion (512) configured to compensate for a load difference between different clock signal lines. An orthographic projection of the load adjusting portion (512) of the at least one connecting line (51) on the base substrate (101) is at least partially overlapped with an orthographic projection of at least one clock signal line on the base substrate (101).

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes a base substrate and a scan line, a data line, a power supply line, a sensing line, a pixel driving circuit and a light-emitting unit that are sequentially stacked on the base substrate. The array substrate also includes a gate layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first electrode of the storage capacitor is at least disposed at the first conductive layer, and the second electrode of the storage capacitor is at least disposed at the second conductive layer. The data line, the power supply line, and the sensing line are disposed at the third conductive layer.

Abstract: A gate driving circuit and a method for driving a gate driving circuit, a display panel, and a display device are provided. The gate driving circuit includes M groups of shift register units, and each group includes one first shift register unit and N?1 second shift register units. The first noise reduction of the first shift register unit performs noise reduction under control of the second node. The second noise reduction circuit of the second shift register units performs noise reduction under control of the second node. In a same group of shift register units, the first shift register unit and the second shift register units share a same second node. A first input signal and a second input signal received by a Kth group of shift register units are a shift signal of a first shift register unit in a (K?2)th group of shift register units.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first transmission circuit and a first input-output unit. The first transmission circuit is electrically connected to a blanking pull-up node and a first pull-up node. The first input-output unit includes an output circuit, a first pull-down control circuit, and a first pull-down auxiliary control circuit.

Abstract: A pixel circuit includes: a driving sub-circuit, a sensing sub-circuit, a light-emitting control sub-circuit, a sensing control sub-circuit, a light-emitting device and a sensing terminal. The driving sub-circuit includes a first terminal and a second terminal coupled to the light-emitting device, and is configured to write a data signal into the driving sub-circuit in response to a first scan signal and control an electrical signal flowing through the driving sub-circuit according to the data signal. The sensing sub-circuit is configured to connect the second terminal to the sensing terminal in response to a second scan signal. The light-emitting control sub-circuit is configured to connect a first voltage terminal to the first terminal in response to a light-emitting control signal. The sensing control sub-circuit is configured to connect a second voltage terminal to the first terminal in response to a sensing control signal provided by a sensing control terminal.

Abstract: Embodiments of the present disclosure provide a shift register, a gate drive circuit and a display device. The shift register includes a light emitting drive output module configured to supply a first voltage of a first power supply terminal to a light emitting control drive signal output terminal in response to control of a voltage at a third node, to supply a second voltage of a second power supply terminal to the light emitting control drive signal output terminal in response to control of a voltage at a second node, and to supply a second voltage of a second power supply terminal to the light emitting control drive signal output terminal in response to control of the second voltage at the second power supply terminal.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a display area and a bonding area connected to the display area. The display area includes multiple data signal lines extending in a second direction, multiple first transfer connection electrodes extending in a first direction, multiple third transfer connection electrodes extending in the second direction, and multiple sub-pixels arranged in an array, at least some of the first transfer connection electrodes are respectively connected to the multiple data signal lines and are respectively connected to at least some of the third transfer connection electrodes, and the end of each third transfer connection electrode connected to a first transfer connection electrode is connected to the bonding area; lengths of the multiple data signal lines, which extend in the second direction, are not exactly the same; and the multiple sub-pixels form a plurality of pixels arranged in an array.

Abstract: A shift register circuit includes an input sub-circuit, an output sub-circuit, a control sub-circuit and a compensation sub-circuit. The input sub-circuit is configured to, under control of a first input signal received at a first input signal terminal, transmit the first input signal to a pull-up node. The output sub-circuit is configured to transmit a first clock signal received at a first clock signal terminal to a first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal received at a first control signal terminal. The compensation sub-circuit is configured to transmit a voltage at a seventh node to the pull-up node under control of a seventh clock signal received at a seventh clock signal terminal.

Abstract: The present disclosure provides a signal selection circuit and a signal selection method of a display panel, and a display device. The display panel has N regions and includes pixel driving circuits and M gate driving circuits for providing M gate driving signals to the pixel driving circuits; each gate driving circuit includes N gate driving sub-circuits, each of which is configured to provide one gate driving signal to the pixel driving circuits in one region; M?2, N?2, and M and N are integers; the signal selection circuit includes: M frame start signal lines, each of which is configured to provide a frame start signal for one gate driving circuit; and a selection sub-circuit configured to output frame start signals written by the frame start signal lines to the gate driving sub-circuits corresponding to the regions of the display panel according to a preset sequence.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein the first sub-circuit includes a first input circuit and a first output circuit; the second sub-circuit includes a second input circuit and a second output circuit; the leakage prevention circuit is configured to control a level of a leakage prevention node under control of the level of the first node, so as to turn off a circuit connected between the first node and the leakage prevention node; and the blanking input sub-circuit is connected to the first node and the second node, and is configured to receive a selection control signal and a first clock signal, and control the level of the first node and the level of the second node.

Abstract: The present disclosure provides a display device, a gate drive circuit, a shift register unit and a driving method thereof. The shift register unit includes an input subcircuit configured to control a voltage at the first node under voltage control of the input control end; a signal output subcircuit configured to control disconnection and conduction between the clock signal ends and respective signal output ends under voltage control of the first node; a first control subcircuit configured to control the voltage at the first node under voltage control of the first control signal end.

Abstract: Embodiments of the present disclosure provide a shift register, a gate drive circuit and a display device. The shift register includes a light emitting drive output module configured to supply a first voltage of a first power supply terminal to a light emitting control drive signal output terminal in response to control of a voltage at a third node, to supply a second voltage of a second power supply terminal to the light emitting control drive signal output terminal in response to control of a voltage at a second node, and to supply a second voltage of a second power supply terminal to the light emitting control drive signal output terminal in response to control of the second voltage at the second power supply terminal.

Abstract: The present disclosure provides a display substrate and a display device, and belongs to the field of display technology. The display substrate of the present disclosure has a display region, and includes a base and a plurality of data lines and a plurality of fan-out traces on the base; each of the plurality of data lines is connected to a corresponding one of the plurality of fan-out traces at a connection node in the display region; and at least one of the plurality of data lines is connected to a corresponding fan-out trace at a plurality of connection nodes.

Abstract: Disclosed is a display panel including a base substrate (101), and a gate drive circuit (40), a plurality of clock signal lines, and a plurality of connecting lines (51) that are disposed on the base substrate (101). The plurality of clock signal lines are located on a side of the gate drive circuit (40) along a first direction (X) and are arranged in sequence. Each connecting line (51) is electrically connected with the gate drive circuit (40) and a clock signal line. At least one connecting line (51) includes a load adjusting portion (512) configured to compensate for a load difference between different clock signal lines. An orthographic projection of the load adjusting portion (512) of the at least one connecting line (51) on the base substrate (101) is at least partially overlapped with an orthographic projection of at least one clock signal line on the base substrate (101).

Abstract: A pixel circuit and a driving method thereof, and a display device are disclosed. The pixel circuit includes a driving circuit, a data writing circuit, a reset circuit, a light-emitting control circuit and a light-emitting element. The driving circuit includes a control terminal, a first terminal and a second terminal; the data writing circuit is connected to a first node to apply a data voltage; the reset circuit is connected to the first node to apply a reference voltage. The pixel circuit further includes a partition control circuit, which is connected to the first node and the control terminal, and is configured to apply the data voltage and the reference voltage to the control terminal; the reset circuit is connected to one of the first terminal and the second terminal of the driving circuit, and the reset circuit is further configured to apply an initialization voltage to the driving circuit.

Abstract: Provided is a display panel. The display panel includes: a substrate; a plurality of first control lines and a plurality of second control lines on a side of the substrate; and a plurality of subpixels arranged in an array on the side of the substrate, wherein at least two of the plurality of subpixels share a first node; wherein the subpixel includes a first circuit and a second circuit, the first circuit and the second circuit being configured to control a voltage at the first node in response to a first control signal and a second control signal; wherein in the display panel, a sum of a number of the plurality of first control lines and a number of the plurality of second control lines is less than or equal to a number of the subpixels in a column direction.

Abstract: The present disclosure provides a pixel circuit, a display panel and a display apparatus, belongs to the field of display technology, and can solve a problem that a current time for compensating a threshold voltage is limited, and is easily affected by a sub-threshold voltage. The pixel circuit includes a reset sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, a sub-threshold compensation sub-circuit, a driving transistor, a first storage capacitor, a first light emitting control sub-circuit, a second light emitting control sub-circuit and a light emitting device; the sub-threshold compensation sub-circuit is configured to store a voltage of a fourth node and compensate a sub-threshold of the driving transistor by using the voltage of the fourth node; the fourth node is a connection point between the sub-threshold compensation sub-circuit, a second electrode of the driving transistor, the data writing sub-circuit and the second light emitting control sub-circuit.

Abstract: A display substrate includes N groups of gate driving circuits and a multiplex circuit. Each group of gate driving circuits includes X gate driving circuits, and each gate driving circuit is electrically connected to rows of pixel circuits in a corresponding display zone. The X gate driving circuits are configured to output X scan signals of different functions to the rows of pixel circuits connected thereto. The multiplex circuit is electrically connected to N gate driving circuits of the N groups of gate driving circuits outputting scan signals of the same function, N selection control signal terminals and a start signal terminal. The multiplex circuit is configured to, under at least one selection control signal from at least one selection control signal terminal, select at least one group of gate driving circuits, and transmit a start signal from the start signal terminal to each selected group of gate driving circuits.