Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a base substrate, a plurality of pixel units and a plurality of gate line groups. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the positions of the sensing transistors are closer to the second gate lines, and the positions of the driving transistors are closer to the first gate line, For two sub-pixels close to each other and located in different pixel units in the same row, at least one signal line has a double-layer alignment structure, and the double-layer alignments are electrically connected with each other.

Abstract: A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node; an output sub-circuit configured to output signal under control of the first node; a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point.

Abstract: A display substrate includes an underlay substrate and a plurality of pixel unit groups. The plurality of pixel unit groups are located in a display region of the underlay substrate. At least one pixel unit group includes a plurality of sub-pixel groups, wherein at least one sub-pixel group includes a pixel circuit. The pixel circuit includes a first sub-pixel circuit, a second sub-pixel circuit, and a light emitting control sub-circuit. The first sub-pixel circuit and the second sub-pixel circuit are both electrically connected to the light emitting control sub-circuit. The light emitting control sub-circuit is configured to control a first light emitting element electrically connected to the first sub-pixel circuit to emit light, and to control a second light emitting element electrically connected to the second sub-pixel circuit to emit light.

Abstract: A shift register circuit includes an input sub-circuit, an output sub-circuit, a control sub-circuit and a compensation sub-circuit. The input sub-circuit is configured to, under control of a first input signal received at a first input signal terminal, transmit the first input signal to a pull-up node. The output sub-circuit is configured to transmit a first clock signal received at a first clock signal terminal to a first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal received at a first control signal terminal. The compensation sub-circuit is configured to transmit a voltage at a seventh node to the pull-up node under control of a seventh clock signal received at a seventh clock signal terminal.

Abstract: Disclosed is a shift register (200) including a first input sub-circuit (210), configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node (Q) in a blanking period of time of a frame; a second input sub-circuit (220), configured to receive a second input signal from a second input terminal and output a display output control signal to the first node (Q) in a display period of time of the frame; an output sub-circuit (230), configured to output a composite output signal via an output terminal (OUT) under control of the first node (Q), the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A display substrate includes N groups of gate driving circuits and a multiplex circuit. Each group of gate driving circuits includes X gate driving circuits, and each gate driving circuit is electrically connected to rows of pixel circuits in a corresponding display zone. The X gate driving circuits are configured to output X scan signals of different functions to the rows of pixel circuits connected thereto. The multiplex circuit is electrically connected to N gate driving circuits of the N groups of gate driving circuits outputting scan signals of the same function, N selection control signal terminals and a start signal terminal. The multiplex circuit is configured to, under at least one selection control signal from at least one selection control signal terminal, select at least one group of gate driving circuits, and transmit a start signal from the start signal terminal to each selected group of gate driving circuits.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output an output blanking output control signal; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal; a selection sub-circuit, having a first terminal connected to the second input sub-circuit, a second terminal connected to the first input sub-circuit, and a third terminal connected to a first node, configured to control a potential of the first node according to the display output control signal and the blanking output control signal; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node.

Abstract: A display substrate has a display area including a plurality of sub-display areas. The display substrate includes a base, a plurality of columns of pixels, a plurality of first and second power lines disposed on the base. At least two columns of pixels are disposed in each sub-display area, and each column of pixels includes at least three columns of sub-pixels. At least one first power line is disposed in each sub-display area and configured to provide a first power signal to all sub-pixels in a sub-display area. The second power lines are configured to provide second power signals to all sub-pixels. A plurality of columns of sub-pixels are disposed between any two adjacent power lines, and any first and second power lines are each arranged between two adjacent columns of sub-pixels emitting light of a first color and sub-pixels emitting light of a second color.

Abstract: A voltage supply circuit, a voltage supply method, a voltage supply module and a display device are provided. The voltage supply circuit includes a first node control circuit, a first control node control circuit, a second node control circuit and a driving voltage output circuit. The first node control circuit controls a potential of the first node; the first control node control circuit controls the potential of the first control node; the second node control circuit controls a potential of the second node; the driving voltage output circuit is electrically connected to the second node, the driving voltage output terminal and the initial voltage terminal respectively, and is configured to control the driving voltage output terminal to output a driving voltage according to the initial voltage provided by the initial voltage terminal under the control of the potential of the second node.

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof and a display device. The display substrate includes: a base substrate; a signal line on the base substrate; a thin film transistor on the base substrate, wherein the thin film transistor is electrically connected to the signal line, and the thin film transistor includes: an active layer, a first insulating layer on a side of the active layer away from the base substrate, a gate on a side of the first insulating layer away from the base substrate, and a source and a drain each electrically connected to the active layer; and a semiconductor structure comprising a semiconductor layer, wherein the semiconductor layer is in a same layer as the active layer, and the semiconductor layer is spaced apart from the signal line.

Abstract: Disclosed are a display substrate and a display apparatus, the display substrate includes a transparent region and a pixel region, the pixel region includes a plurality of light emitting devices, the plurality of light emitting devices include a first light emitting device, an orthographic projection of a first anode layer of the first light emitting device on a plane of the display substrate is partially overlapped with an orthographic projection of the transparent region on the plane of the display substrate, and an orthographic projection of a second anode layer of the first light emitting device on the plane of the display substrate is within a range of an orthographic projection of the pixel region on the plane of the display substrate.

Abstract: A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.

Abstract: A pixel circuit includes: a driving sub-circuit, a sensing sub-circuit, a light-emitting control sub-circuit, a sensing control sub-circuit, a light-emitting device and a sensing terminal. The driving sub-circuit includes a first terminal and a second terminal coupled to the light-emitting device, and is configured to write a data signal into the driving sub-circuit in response to a first scan signal and control an electrical signal flowing through the driving sub-circuit according to the data signal. The sensing sub-circuit is configured to connect the second terminal to the sensing terminal in response to a second scan signal. The light-emitting control sub-circuit is configured to connect a first voltage terminal to the first terminal in response to a light-emitting control signal. The sensing control sub-circuit is configured to connect a second voltage terminal to the first terminal in response to a sensing control signal provided by a sensing control terminal.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, a plurality of pixels, a plurality of gate lines and a plurality of data lines, wherein the base substrate has a plurality of transparent regions and a plurality of display regions; the pixels are on the base substrate and within the display regions; each pixel includes a plurality of sub pixels; the sub pixels of each pixel are divided into two rows of sub pixels; the gate lines and the data lines are on the base substrate; the sub pixels of a first pixel are connected with the same gate line; the gate line connected with the sub pixels of the first pixel is between the two rows of sub pixels of the first pixel; and the first pixel is any one of the plurality of pixels.

Abstract: The present disclosure provides a signal selection circuit and a signal selection method of a display panel, and a display device. The display panel has N regions and includes pixel driving circuits and M gate driving circuits for providing M gate driving signals to the pixel driving circuits; each gate driving circuit includes N gate driving sub-circuits, each of which is configured to provide one gate driving signal to the pixel driving circuits in one region; M?2, N?2, and M and N are integers; the signal selection circuit includes: M frame start signal lines, each of which is configured to provide a frame start signal for one gate driving circuit; and a selection sub-circuit configured to output frame start signals written by the frame start signal lines to the gate driving sub-circuits corresponding to the regions of the display panel according to a preset sequence.

Abstract: A light-emitting control shift register includes an input circuit, a pulse width adjustment circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit. The input circuit is configured to output a signal of a first signal input terminal. The pulse width adjustment circuit is configured to transmit the signal output from the input circuit to a pull-up node, and is further configured to output a signal of a second clock signal terminal to the pull-up node. The pull-up circuit is configured to output a voltage of a first voltage terminal to a signal output terminal. The pull-down control circuit is configured to output the voltage of the first voltage terminal, and is further configured to output a voltage of a second voltage terminal. The pull-down circuit is configured to pull down a voltage of the signal output terminal to the voltage of the second voltage terminal.

Abstract: The disclosure provides a display substrate, which has a display region and a peripheral region, and includes a base substrate, a plurality of sub-pixels, a first power signal line and a second power signal line at least partially located in the display region, a first power signal bus and a second power signal bus located in the peripheral region; the sub-pixels are located in the display region; the first power signal line and the second power signal line are electrically connected to the first power signal bus and the second power signal bus, respectively; the second power signal bus includes a first part disposed on a side of the first power signal bus close to the display region, and a second part disposed on a side of the first power signal bus away from the display region, so as to at least partially surround the first power signal bus.

Abstract: A shift register includes a first scan unit including a first input circuit and a first output circuit, and a second scan unit including a second input circuit, a second output circuit, and a fourth transistor. The first input circuit is electrically connected to an input signal terminal and a first pull-up node. The first output circuit is electrically connected to the first pull-up node, a first clock signal terminal, a second clock signal terminal, a shift signal terminal, and a first scan signal terminal. The second input circuit is electrically connected to the input signal terminal and a second pull-up node. The second output circuit is electrically connected to the second pull-up node, a third clock signal terminal, and a second scan signal terminal. The fourth transistor is electrically connected to the second pull-up node, a sub-clock signal terminal, and a dummy shift signal terminal.

Abstract: A profiled display panel, including a display area. The display area includes a plurality of display sub-areas; a plurality of cascade signal lines for coupling adjacent two of the gate driving sub-circuits. At least one cascade signal line includes a first cascade trace extending in a first direction and a second cascade trace extending in a second direction. The first cascade trace includes a plurality of first conductive patterns arranged on a first conductive layer and second conductive pattern arranged on a second conductive layer. The plurality of first conductive patterns are electrically connected to the second conductive pattern; and the second cascade trace includes a third conductive pattern arranged on the first conductive layer.

Abstract: A display substrate includes a plurality of pixel circuits, and the pixel circuits each include a sensing circuit and a light-emitting control circuit. In a second direction, adjacent three rows of pixel circuits are a first row of pixel circuits, a second row of pixel circuits and a third row of pixel circuits. A region between the first row of pixel circuits and the second row of pixel circuits is a first gap region. In the first row of pixel circuits and the second row of pixel circuits, a sensing circuit of each pixel circuit is closer to the first gap region than a light-emitting control circuit of the pixel circuit, and sensing signal terminals of sensing circuits of two pixel circuits in a same column are a same signal terminal.