Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a base substrate, a plurality of pixel units and a plurality of gate line groups. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the positions of the sensing transistors are closer to the second gate lines, and the positions of the driving transistors are closer to the first gate line, For two sub-pixels close to each other and located in different pixel units in the same row, at least one signal line has a double-layer alignment structure, and the double-layer alignments are electrically connected with each other.

Abstract: A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.

Abstract: A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node, wherein the second input sub-circuit includes an isolation sub-circuit, wherein the isolation sub-circuit is set between the first node and the blank-control node; an output sub-circuit configured to output signal under control of the first node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point. The anti-leak sub-circuit includes a second anti-leak transistor connected to the isolation sub-circuit.

Abstract: The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a substrate, and a compensation electrode, an auxiliary electrode, a light-emitting functional layer, and a cathode layer arranged on one side of the substrate. The auxiliary electrode is arranged on one side of the compensation electrode away from the substrate, and coupled to the compensation electrode. A first notch is formed in a side surface of the auxiliary electrode, and at least a part of the first notch extends in a direction parallel to the substrate. The light-emitting functional layer is arranged on one side of the auxiliary electrode away from the substrate, and interrupted at the first notch. The cathode layer is arranged on one side of the light-emitting functional layer away from the substrate, and coupled to the auxiliary electrode at the first notch.

Abstract: A display substrate and a display device. The display substrate includes a base substrate, and a plurality of pixel units and a plurality of scanning lines on the base substrate. Each pixel unit includes a plurality of sub-pixels and a light shielding layer, the plurality of sub-pixels is arranged in sequence in a first direction, each sub-pixel includes a sub-pixel driving circuitry and a light-emitting element coupled to each other, and the sub-pixel driving circuitry is configured to provide a driving signal to the light-emitting element. At least a part of the light shielding layer is arranged between the sub-pixel driving circuitry and the base substrate. Each scanning line includes at least a part extending in the first direction, is coupled to a corresponding sub-pixel driving circuitry, and is arranged at a same layer as the light shielding layer.

Abstract: A scan driving circuit includes shift registers and clock signal lines. A shift register includes: an output circuit electrically connected to a scan input signal terminal and a pull-up node; a black frame insertion circuit electrically connected to a first clock signal terminal, a black frame insertion input signal terminal, a first voltage signal terminal, a second clock signal terminal and the pull-up node; and an output circuit electrically connected to the pull-up node, a third clock signal terminal, a shift signal terminal, a fourth clock signal terminal and a first output signal terminal. The shift registers include first shift registers and second shift registers. Third and fourth clock signal terminals of a first shift register are electrically connected to a same clock signal line. Third and fourth clock signal terminals of a second shift register are electrically connected to different clock signal lines.

Abstract: A display substrate includes a plurality of pixel circuits, and the pixel circuits each include a sensing circuit and a light-emitting control circuit. In a second direction, adjacent three rows of pixel circuits are a first row of pixel circuits, a second row of pixel circuits and a third row of pixel circuits. A region between the first row of pixel circuits and the second row of pixel circuits is a first gap region. In the first row of pixel circuits and the second row of pixel circuits, a sensing circuit of each pixel circuit is closer to the first gap region than a light-emitting control circuit of the pixel circuit, and sensing signal terminals of sensing circuits of two pixel circuits in a same column are a same signal terminal.

Abstract: A display substrate includes an underlay substrate and a plurality of pixel unit groups. The plurality of pixel unit groups are located in a display region of the underlay substrate. At least one pixel unit group includes a plurality of sub-pixel groups, wherein at least one sub-pixel group includes a pixel circuit. The pixel circuit includes a first sub-pixel circuit, a second sub-pixel circuit, and a light emitting control sub-circuit. The first sub-pixel circuit and the second sub-pixel circuit are both electrically connected to the light emitting control sub-circuit. The light emitting control sub-circuit is configured to control a first light emitting element electrically connected to the first sub-pixel circuit to emit light, and to control a second light emitting element electrically connected to the second sub-pixel circuit to emit light.

Abstract: A display substrate and a display panel are provided. The display substrate includes: a base substrate; and a plurality of sub-pixels. Each sub-pixel includes a light-emitting element and a pixel circuit; the pixel circuit includes a driving circuit, a data writing circuit, a first control circuit, a second control circuit, and a light-emitting control circuit; the driving circuit is configured to control the driving current flowing through the light-emitting element; the light-emitting control circuit is configured to apply the driving current to the light-emitting element; the first control circuit is configured to write a reference voltage into the driving circuit; the second control circuit is configured to write an initial voltage into the first electrode of the light-emitting element; and orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of sub-pixels on the base substrate are mirror-symmetrical.

Abstract: A display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a plurality of stages of shift registers including at least one first shift register and at least one second shift register, and a plurality of clock signal lines including at least one first sub-clock signal line and at least one second sub-clock signal line. Each shift register includes a first sub-circuit and a second sub-circuit. A first sub-clock signal line in the at least one first sub-clock signal line is electrically connected to a first sub-circuit in a first shift register in the at least one first shift register. A second sub-clock signal line in the at least one second sub-clock signal line is electrically connected to one sub-circuit of a first sub-circuit and a second sub-circuit in a second shift register in the at least one second shift register.

Abstract: A display substrate and a display panel are provided. The display substrate includes: a base substrate; and a plurality of sub-pixels. Each sub-pixel includes a light-emitting element and a pixel circuit; the pixel circuit includes a driving circuit, a data writing circuit, a first control circuit, a second control circuit, and a light-emitting control circuit; the driving circuit is configured to control the driving current flowing through the light-emitting element; the light-emitting control circuit is configured to apply the driving current to the light-emitting element; the first control circuit is configured to write a reference voltage into the driving circuit; the second control circuit is configured to write an initial voltage into the first electrode of the light-emitting element; and orthographic projections of at least part of pixel circuits of every two adjacent sub-pixels in a same row of sub-pixels on the base substrate are mirror-symmetrical.

Abstract: A display panel has a display area and a fan-out region. The display panel includes: a substrate; a scan driving circuit including shift registers and clock signal lines, sub-pixels and signal transmission lines that are located in the display area; and a power supply voltage bus and connection lines that are located in the fan-out region. The sub-pixels are arranged in rows and columns, sub-pixels in a column are arranged along a second direction. A signal transmission line is electrically connected to column(s) of sub-pixels. The connection lines include first connection sub-lines, second connection sub-lines and third connection sub-lines that extend along the second direction and are located away from the sub-pixels. A first connection sub-line, a second connection sub-line and a third connection sub-line are electrically connected to the signal transmission line, the power supply voltage bus, and a clock signal line, respectively.

Abstract: The present disclosure provides a shift register unit, including: a first sensing control input circuit and at least one first output circuit; the shift register unit further includes: a first voltage control circuit, a first sensing input leakage prevention circuit and a first current limiting circuit; the first sensing control input circuit is connected to a first pull-up node through the first sensing input leakage prevention circuit, the first sensing control input circuit is connected to the first sensing input leakage prevention circuit at a first sensing input leakage prevention node connected to a first voltage control node, the first sensing input leakage prevention circuit is connected to the clock control signal input terminal and is configured to control on/off between the first sensing input leakage prevention node and the first pull-up node; the first current limiting circuit is connected to the first voltage control node.

Abstract: The present disclosure relates to an array substrate and a display panel, the array substrate including at least one pixel unit and a first gate line, each pixel unit including at least one sub-pixel, each sub-pixel including a pixel circuit, the pixel circuit including a first transistor, the first gate line being electrically connected to a gate of the first transistor through a first connecting part, the first connecting part and the first gate line being located in different conductive layers from each other. The array substrate provided in some embodiments of the present disclosure eliminates the risk of pixel circuit transistor damage caused by electrostatic conduction of the gate line by means of the measure of same layer separation and cross layer connection of the gate of the transistor and the corresponding gate line.

Abstract: A display panel and a display device are provided, the first signal line extends from the display region to the electrostatic discharge region in a first direction, and provides a first display signal to the sub-pixels; the electrostatic discharge units are arranged in the first direction, each electrostatic discharge unit includes a sub electrostatic discharge unit, each sub electrostatic discharge unit includes an electrostatic discharge circuit and a first conductor, the electrostatic discharge circuit is connected to the first signal line and the first conductor, and charges on the first signal line move towards the first conductor; the electrostatic discharge units include two adjacent electrostatic discharge units in a second direction perpendicular to the first direction, orthographic projections of the two adjacent electrostatic discharge units on a plane parallel to the first direction are not overlapped, and on a plane parallel to the second direction are overlapped.

Abstract: Provided in the present disclosure are a display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of display units, each display unit comprising a display area and a transparent area, and the display area comprising a plurality of sub-pixels; each sub-pixel comprises a second metal layer and a third metal layer, the second metal layer comprising a first scanning line and a second scanning line defining a display row, the third metal layer comprising a first power source line, a second power source line, a compensation line, and a data line defining the plurality of sub-pixels; the first power source line, the second power source line, the compensation line, and the data line all comprise a vertical linear section and a horizontal polyline section.

Abstract: Provided is a gate driver circuit. The gate driver circuit is applicable to a display panel, wherein the display panel includes a plurality of rows of pixels; the gate driver circuit including at least one gate driver sub-circuit; wherein the gate driver sub-circuit includes: at least two shift register groups, wherein each shift register group includes a plurality of shift register units; at least two first dummy units, wherein the at least two first dummy units are respectively coupled to a same input enable terminal and the at least two shift register groups; and at least two second dummy units, wherein the at least two second dummy units are coupled to the at least two shift register groups.

Abstract: Disclosed is a display panel including a base substrate (101), and a gate drive circuit (40), a plurality of clock signal lines, and a plurality of connecting lines (51) that are disposed on the base substrate (101). The plurality of clock signal lines are located on a side of the gate drive circuit (40) along a first direction (X) and are arranged in sequence. Each connecting line (51) is electrically connected with the gate drive circuit (40) and a clock signal line. At least one connecting line (51) includes a load adjusting portion (512) configured to compensate for a load difference between different clock signal lines. An orthographic projection of the load adjusting portion (512) of the at least one connecting line (51) on the base substrate (101) is at least partially overlapped with an orthographic projection of at least one clock signal line on the base substrate (101).

Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a base substrate, a plurality of pixel units and a plurality of gate line groups. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the positions of the sensing transistors are closer to the second gate lines, and the positions of the driving transistors are closer to the first gate line, For two sub-pixels close to each other and located in different pixel units in the same row, at least one signal line has a double-layer alignment structure, and the double-layer alignments are electrically connected with each other.

Abstract: A shift register is provided, which includes a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, and a shift register circuit, and a twenty-ninth transistor. The blanking input circuit may provide a blanking input signal to a first control node according to a second clock signal. and comprise a first transistor The blanking control circuit may provide a first clock signal to a second control node and maintain a voltage difference between the first control node and the second control node, according to a voltage of the first control node. comprise a second transistor. The blanking pull-down circuit may provide a voltage of the second control node to a pull-down node according to the a first clock signal and comprise a third transistor and a third leakage-preventative transistor. The shift register circuit may provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal according to a voltage of the pull-down node.