Abstract: A display substrate includes: a base substrate; a first conductive pattern arranged on the base substrate; a first insulation layer arranged at a side of the first conductive pattern away from the base substrate; a second conductive pattern arranged at a side of the first insulation layer away from the base substrate; a second insulation layer arranged at a side of the second conductive pattern away from the base substrate; and a third conductive pattern arranged at a side of the second insulation layer away from the base substrate. The third conductive pattern and the first conductive pattern together serve as a first electrode plate of the capacitor, and the second conductive pattern serves as a second electrode plate of the capacitor.

Abstract: A shift register, a gate drive circuit and a driving method therefor. The shift register includes a display pre-charge reset subcircuit, a sensing pre-charge reset subcircuit, a pull-down control subcircuit, an output subcircuit, a sensing cascade subcircuit and a black frame insertion cascade subcircuit. The display pre-charge reset subcircuit is configured to provide a signal of a first power supply end for a pull-up node under control of a first signal input end and provide a signal of a second power supply end to the pull-up node under control of a reset signal end; the sensing pre-charge reset subcircuit is configured to provide a signal of a first clock signal end to the pull-up node under control of the sensing cascade node and the first clock signal end, and provide a signal of the second power supply end to the pull-up node under control of a total reset end.

Abstract: The present disclosure provides a shift register unit, including a detection signal input sub-circuit, a display signal input sub-circuit, an output circuit, a pull-down control circuit and a signal output terminal, the output circuit includes a pull-up sub-circuit and a pull-down sub-circuit, the pull-down control circuit includes a selection sub-circuit and a plurality of pull-down control sub-circuits. The present disclosure further provides a gate driving circuit, a display panel and a driving method for driving the display panel. The shift register unit has a simple structure and a long service life.

Abstract: A display substrate has a display area and a peripheral area. The display substrate includes a plurality of sub-pixels, a plurality of groups of gate scan signal lines, and a plurality of groups of data lines. Each group of gate scan signal lines includes at least one gate scan signal line, each group of data lines includes n data lines, and the plurality of sub-pixels are arranged in an array; and n is greater than or equal to 2. A group of gate scan signal lines is electrically connected to n rows of sub-pixels. A column of sub-pixels is electrically connected to a group of data lines, and includes a plurality of groups of sub-pixels. Each group of sub-pixels includes n sub-pixels. The n sub-pixels are respectively electrically connected to n data lines in the group of data lines to which this column of sub-pixels is electrically connected.

Abstract: A display substrate, a manufacturing method therefor, and a display device. The display substrate comprises multiple display units, and each display unit includes a display area and a transparent area; each display area is provided with a first power supply line and a second power supply line along a first direction, the display area is provided with a first scan signal line, a second scan signal line, a second scan connection line, and a first scan connection line along a second direction, and the second scan connection line and the second scan signal line are connected into a first annular structure; each display area is further provided with a third scan connection line, and the third scan connection line, the first scan connection line, and the first scan signal line are connected into a second annular structure.

Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a base substrate, a plurality of pixel units and a plurality of gate line groups. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the positions of the sensing transistors are closer to the second gate lines, and the positions of the driving transistors are closer to the first gate line, For two sub-pixels close to each other and located in different pixel units in the same row, at least one signal line has a double-layer alignment structure, and the double-layer alignments are electrically connected with each other.

Abstract: A shift register includes a first scan unit, a leakage prevention unit, and a leakage prevention input unit. The first scan unit includes a first input circuit configured to transmit an input signal to a first pull-up node. The leakage prevention input unit is configured to: in response to a first voltage signal received at a first voltage signal terminal, transmit the first voltage signal to a leakage prevention input node; and in response to a second voltage signal received at a second voltage signal terminal, transmit the second voltage signal to the leakage prevention input node. The first voltage signal and the second voltage signal are mutually inverted signals. The leakage prevention unit is configured to transmit one of the first voltage signal and the second voltage signal from the leakage prevention input node to a first leakage prevention node.

Abstract: A display panel includes a substrate, a pad, an auxiliary electrode layer, a data line layer, a first electrode layer, a light emitting layer, and a second electrode layer. The substrate has a display area and a peripheral area. The pad is disposed on a side of the substrate and located in the peripheral area. The auxiliary electrode layer is disposed on the same side of the substrate as the pad; the data line layer is disposed on a same layer as the auxiliary electrode layer; the first electrode layer is disposed on a side of the auxiliary electrode layer facing away from the substrate; the light emitting layer is disposed on a side of the first electrode layer facing away from the substrate; and the second electrode layer is disposed on a side of the light emitting layer facing away from the substrate and connected to the auxiliary electrode layer.

Abstract: A display apparatus, a display panel, and a driving method thereof, and a method of detecting a pixel circuit are described. The display panel includes a pixel unit and a detection apparatus, and the pixel unit includes a pixel circuit and a light-emitting element. The pixel circuit includes a first transistor, a second transistor, a driving transistor, and a storage capacitor. The detection device is configured to: turn off the first transistor and the second transistor, and detect an amount of current leakage of the driving transistor leaked through the sensing line to obtain a first current leakage parameter; detect a first characteristic parameter of the driving transistor to obtain a first reference characteristic parameter; and determine a first target characteristic parameter according to the first current leakage parameter and the first reference characteristic parameter.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a gate driving circuit including a first transistor; a base substrate; a functional layer located on a side of the base substrate, a material of the functional layer is a thermal conductive material, and the functional layer includes a first functional portion; an active layer located on a side of the functional layer away from the base substrate, the active layer includes a first active portion including at least one first active sub-portion which is configured to form a channel region of the first transistor; a second conductive layer located on a side of the active layer away from the base substrate, the second conductive layer includes a first conductive portion connected to the first functional portion through a first via hole.

Abstract: A pixel circuit, a driving method of pixel circuit, and a display device are provided. The pixel circuit includes: a light emitting device, a driving sub-circuit, an energy storage sub-circuit, a data writing sub-circuit and a pull-down sub-circuit; the data writing sub-circuit is configured to control a voltage signal on a data line to be written into a control end of the driving sub-circuit in response to a data writing control signal; a first end of the driving sub-circuit is electrically connected to a target node, a second end of the driving sub-circuit is electrically connected to a power supply voltage, and the driving sub-circuit is configured to control a conduction of the driving sub-circuit under a control of a voltage on a control end of the driving sub-circuit.

Abstract: A shift-register unit circuit includes a first input sub-circuit configured to have a display-input terminal to receive a display-input signal, and to provide a display output-control signal to a first node; a second input sub-circuit configured to have a blank-input terminal to receive a blank-input signal for charging a blank-control node, and to provide a blank output-control signal to the first node; an output sub-circuit configured to output signal under control of the first node; a first control sub-circuit, configured to control a voltage level of a second node under control of the first node; a second control sub-circuit configured to pull down voltage levels of the first node and the output terminal to turn-off voltage levels under control of the second node; and an anti-leak sub-circuit configured to provide a working voltage level to an anti-leak connection point.

Abstract: A shift register unit and a method of driving the shift register unit, a gate driving circuit, and a display device. The shift register unit includes: a first shift register configured to generate a first control output signal (CR1) and a second control output signal (CR2) based on a signal at a first clock signal terminal (CLKD); and a second shift register configured to generate a second output signal (OUT2) based on a signal at a third clock signal terminal (CLKE2), wherein a first pull-down node (PD1_1) of the first shift register is connected to a second pull-down node (PD2_2) of the second shift register, and a second pull-down node (PD1_2) of the first shift register is connected to a first pull-down node (PD2_1) of the second shift register.

Abstract: A shift register unit includes a first input/output unit which includes a first pull-down control circuit and a first auxiliary input circuit, and a second input/output unit which includes a second pull-down control circuit and a second auxiliary input circuit. The first pull-down control circuit controls a level of a first pull-down node. The first auxiliary input circuit is coupled to the first pull-down control circuit and controls the first pull-down control circuit together with a level of a first pull-up node in response to a display control signal and a blanking control signal. The second pull-down control circuit controls a level of a second pull-down node. The second auxiliary input circuit is coupled to the second pull-to down control circuit and controls the second pull-down control circuit together with a level of a second pull-up node in response to the display control signal and the blanking control signal.

Abstract: The present disclose is related to an array substrate. The array substrate may include a base substrate; a driving transistor on the base substrate; an insulating layer on the driving transistor, the insulating layer comprising a via hole above a first electrode of the driving transistor; a conductive portion on the insulating layer; and a light emitting device on the conductive portion and electrically connected to the conductive portion. The conductive portion may be electrically connected to the first electrode of the driving transistor through the via hole. The light emitting device may be above the via hole, and an orthographic projection of the light emitting device on the base substrate may cover an orthographic projection of the via hole on the base substrate.

Abstract: A display substrate includes: a base substrate; a first conductive pattern arranged on the base substrate; a first insulation layer arranged at a side of the first conductive pattern away from the base substrate; a second conductive pattern arranged at a side of the first insulation layer away from the base substrate; a second insulation layer arranged at a side of the second conductive pattern away from the base substrate; and a third conductive pattern arranged at a side of the second insulation layer away from the base substrate. The third conductive pattern and the first conductive pattern together serve as a first electrode plate of the capacitor, and the second conductive pattern serves as a second electrode plate of the capacitor.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output an output blanking output control signal; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal; a selection sub-circuit, having a first terminal connected to the second input sub-circuit, a second terminal connected to the first input sub-circuit, and a third terminal connected to a first node, configured to control a potential of the first node according to the display output control signal and the blanking output control signal; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node.

Abstract: Provided are a pixel structure, a method for driving the same and a display substrate. The pixel structure includes N pixel circuits and a power writing control circuit, N?2 and N is an integer. Each pixel circuit includes a pixel driving sub-circuit and a light-emitting device. The power writing control circuit provides, according to a voltage regulation control signal, a first power voltage for each pixel circuit in a light-emitting phase. The pixel driving sub-circuit provides, according to a data voltage signal, a driving current for the light-emitting device under the control of a first scanning signal. Light-emitting devices in the pixel circuits are sequentially connected in series, a first electrode of the light-emitting device in the first pixel circuit is connected to the power writing control circuit, a second electrode of the light-emitting device in the Nth pixel circuit is connected to a second power terminal.

Abstract: A driving backplane includes a base substrate, and data lines, a first gate line, a second gate line and pixel driving circuits that are disposed on the base substrate. The first gate line and the second gate line are adjacent. Each pixel driving circuit includes a first transistor including an active layer. The active layer includes an active portion, a first conductive portion and a second conductive portion. Active portions of first transistors further include first contact portions. The pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit that are coupled to a data line and the first gate line. A first conductive portion in the first pixel driving circuit and a first conductive portion in the second pixel driving circuit are in contact through a first contact portion, and are coupled to the data line through the first contact portion.

Abstract: A shift register, a gate drive circuit and a driving method therefor. The shift register includes a display pre-charge reset subcircuit, a sensing pre-charge reset subcircuit, a pull-down control subcircuit, an output subcircuit, a sensing cascade subcircuit and a black frame insertion cascade subcircuit. The display pre-charge reset subcircuit is configured to provide a signal of a first power supply end for a pull-up node under control of a first signal input end and provide a signal of a second power supply end to the pull-up node under control of a reset signal end; the sensing pre-charge reset subcircuit is configured to provide a signal of a first clock signal end to the pull-up node under control of the sensing cascade node and the first clock signal end, and provide a signal of the second power supply end to the pull-up node under control of a total reset end.