Abstract: A shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit connected to a first input terminal and a first pull-up node, a first output circuit connected to the first pull-up node, a first output terminal and a first clock terminal, and a first pull-down circuit. The second shift register unit comprises a second input circuit connected to a second input terminal and a second pull-up node, and a second output circuit connected to the second pull-up node, a second output terminal and a second clock signal.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node in response to an input signal input; the first control circuit is configured to control a level of the second node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal under control of the level of the first node; and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node.

Abstract: A pixel circuit includes a data line, a sensing line, a first pixel sub-circuit and a second pixel sub-circuit. The first pixel sub-circuit includes a first writing unit, a first sensing unit and a first driving unit. The first driving unit is configured to drive a first light-emitting unit to emit light. The second pixel sub-circuit includes a second writing unit, a second sensing unit and a second driving unit. The second driving unit is configured to drive a second light-emitting unit to emit light. The first writing unit and the second sensing unit are both configured to be connected to a gate driving unit. The second writing unit and the first sensing unit are both configured to be connected to another gate driving unit.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking unit, a first transmission circuit and a first input-output unit. The blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node. The first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node; and the first input-output unit includes a first leakage preventing structure, the first leakage preventing structure is electrically connected to the first pull-up node and a first leakage preventing node respectively, and the leakage preventing structure is configured to control a level of the first leakage preventing node under the control of the level of the first pull-up node to prevent the first pull-up node from leaking.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein the first sub-circuit comprises a first input circuit and a first output circuit; the second sub-circuit comprises a second input circuit and a second output circuit; the leakage prevention circuit is configured to control a level of a leakage prevention node under control of the level of the first node, so as to turn off a circuit connected between the first node and the leakage prevention node; and the blanking input sub-circuit is connected to the first node and the second node, and is configured to receive a selection control signal and a first clock signal, and control the level of the first node and the level of the second node.

Abstract: The present disclosure provides a shift resister unit, a gate driving circuit, a display device, and a method for controlling a shift register unit. The shift register unit incudes a first input sub-circuit, a first output sub-circuit, a first reset sub-circuit, a second input sub-circuit, and a third input sub-circuit. The first input sub-circuit is configured to change a potential of a first node in a first phase. The first output sub-circuit is configured to output a gate driving signal in the first phase and output a compensation driving signal in a second phase. The first reset sub-circuit is configured to reset the first node. The second input sub-circuit is configured to change a potential of a second node in the first phase and maintain the potential of the second node. The third input sub-circuit is configured to change the potential of the first node in the second phase.

Abstract: A display panel and a display device are provided, since a plurality of source ICs (01) are arranged, a large-sized display panel is driven, and since the plurality of source ICs (01) are scattered around a display area (A) along the tangential directions of the edge of the display area (A), that is, the source ICs (01) are distributed according to the shape of the display panel, a distance between the source ICs (01) and the display area (A) is shortened, and thus a narrow bezel design of the display panel is facilitated.

Abstract: A display substrate (100) and a design method therefor, and a display apparatus. The display substrate (100) includes: pixel circuits which are arranged in an array, where the pixel circuits are divided into at least two areas; and data switching circuits (10), which are correspondingly connected to the pixel circuits in the areas by means of data signal lines, wherein a channel width-to-length ratio (W/L) of a switch device in each data switching circuit (10) is positively correlated with a design data load of an area corresponding to the data switching circuit (10). The width-to-length ratios (W/L) of different switch devices can be matched according to different design data loads of different areas.

Abstract: Disclosed are a display substrate and a display device. A display region and a peripheral region are included. The peripheral region includes a plurality of shift registers and a plurality of clock signal lines. The plurality of clock signal lines are arranged side by side in a first direction and include a first clock signal line to a Zth clock signal line, Z?1. The shift registers are connected with gate lines in the display region and the first clock signal line to the Zth clock signal line respectively. There is at least a group of ith clock signal lines satisfying that the ith clock signal lines include X ith clock signal lines which are arranged one by one according to a sequence of connection with shift registers and further include N ith clock signal lines.

Abstract: A pixel circuit, a driving method of pixel circuit, and a display device are provided. The pixel circuit includes: a light emitting device, a driving sub-circuit, an energy storage sub-circuit, a data writing sub-circuit and a pull-down sub-circuit; the data writing sub-circuit is configured to control a voltage signal on a data line to be written into a control end of the driving sub-circuit in response to a data writing control signal; a first end of the driving sub-circuit is electrically connected to a target node, a second end of the driving sub-circuit is electrically connected to a power supply voltage, and the driving sub-circuit is configured to control a conduction of the driving sub-circuit under a control of a voltage on a control end of the driving sub-circuit.

Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a base substrate, a plurality of pixel units and a plurality of gate line groups. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the positions of the sensing transistors are closer to the second gate lines, and the positions of the driving transistors are closer to the first gate line, For two sub-pixels close to each other and located in different pixel units in the same row, at least one signal line has a double-layer alignment structure, and the double-layer alignments are electrically connected with each other.

Abstract: A display panel includes a plurality of rows of sub-pixels and at least one gate driver circuit that are disposed on a base substrate. Each sub-pixel includes a pixel driver circuit and a light-emitting device coupled to the pixel driver circuit, and a gate driver circuit includes a plurality of shift registers that are cascaded and a plurality of control signal lines. A shift register is coupled to a plurality of pixel driver circuits in at least one row of sub-pixels and at least a part of the plurality of control signal lines, and includes a plurality of first thin film transistors that are divided into a plurality of first thin film transistors. At least one thin film transistor group is located in the display region and distributed between adjacent sub-pixels in a same row of sub-pixels.

Abstract: A shift register a first scan unit a leakage prevention unit, and a leakage input unit. The first scan unit includes a first input circuit configured to transmit an input signal to a first pull-up node. The leakage prevention input unit is configured to: in response to a first voltage signal received at a first voltage signal terminal, transmit a the first voltage signal to a leakage prevention input node and in response to a second voltage signal received at a second voltage signal terminal, to transmit the second voltage signal to the leakage prevention input node (M) in The first voltage signal and the second voltage signal are mutually inverted signals. The leakage prevention unit is configured to transmit one of the first voltage signal and the second voltage signal from the leakage prevention input node to a first leakage prevention node.

Abstract: A shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit connected to a first input terminal and a first pull-up node, a first output circuit connected to the first pull-up node, a first output terminal and a first clock terminal, a first pull-down circuit and a unidirectional isolation circuit, and the first output terminal is connected to the first pull-down circuit by the unidirectional isolation circuit. The second shift register unit comprises a second input circuit connected to a second input terminal and a second pull-up node, and a second output circuit connected to the second pull-up node, a second output terminal and a second clock signal, and the second output terminal is connected to a node between the first pull-down circuit and the unidirectional isolation circuit.

Abstract: A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node; the first input circuit includes a first transistor and a first capacitor, and a second electrode of the first capacitor is connected to the first electrode of the first transistor.

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes a base substrate and a scan line, a data line, a power supply line, a sensing line, a pixel driving circuit and a light-emitting unit that are sequentially stacked on the base substrate. The array substrate also includes a gate layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first electrode of the storage capacitor is at least disposed at the first conductive layer, and the second electrode of the storage capacitor is at least disposed at the second conductive layer. The data line, the power supply line, and the sensing line are disposed at the third conductive layer.

Abstract: The present disclosure provides an array substrate, a display panel, a display device and a manufacturing method, for solving the problems in the prior art that the array substrate is larger in number of circuits, the area needed for punching is larger, and the high pixel resolution cannot be achieved easily.

Abstract: A display substrate includes: a base substrate; a first conductive pattern arranged on the base substrate; a first insulation layer arranged at a side of the first conductive pattern away from the base substrate; a second conductive pattern arranged at a side of the first insulation layer away from the base substrate; a second insulation layer arranged at a side of the second conductive pattern away from the base substrate; and a third conductive pattern arranged at a side of the second insulation layer away from the base substrate. The third conductive pattern and the first conductive pattern together serve as a first electrode plate of the capacitor, and the second conductive pattern serves as a second electrode plate of the capacitor.

Abstract: A display panel includes a substrate, a pad, an auxiliary electrode layer, a data line layer, a first electrode layer, a light emitting layer, and a second electrode layer. The substrate has a display area and a peripheral area. The pad is disposed on a side of the substrate and located in the peripheral area. The auxiliary electrode layer is disposed on the same side of the substrate as the pad; the data line layer is disposed on a same layer as the auxiliary electrode layer; the first electrode layer is disposed on a side of the auxiliary electrode layer facing away from the substrate; the light emitting layer is disposed on a side of the first electrode layer facing away from the substrate; and the second electrode layer is disposed on a side of the light emitting layer facing away from the substrate and connected to the auxiliary electrode layer.