Abstract: A display substrate and a preparation method therefor, and a display apparatus. The display substrate includes a base substrate, and a display area and a mounting area provided on the base substrate; the display area includes multiple second pixel circuits, the mounting area includes multiple first pixel circuits, and an area of an orthographic projection of a first pixel circuit on the base substrate is smaller than an area of an orthographic projection of a second pixel circuit on the base substrate.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, and a gate driving circuit and a plurality of signal lines arranged on the base substrate; the plurality of signal lines include a first clock sub-signal line and a second clock sub-signal line; an orthographic projection of the first clock sub-signal line on the base substrate and an orthographic projection of the second clock sub-signal line on the base substrate are arranged side by side, and the first clock sub-signal provided by the first clock sub-signal line is the same as the second clock sub-signal provided by the second clock sub-signal line.

Abstract: The present disclosure provides a shift register unit, a signal generation unit circuit, a driving method and a display device. The shift register unit includes a first node control circuit, a second node control circuit and an output circuit, the first node control circuit is used to control a potential of a first node; the second node control circuit controls a potential of a second node; the output circuit is used to control and maintain the potential of the first node and the potential of the second node, and control to connect the output terminal and the second clock signal terminal under the control of the potential of the first node, and control to connect the input terminal and the second voltage terminal under the control of the potential of the second node.

Abstract: A display panel includes pixel driving circuits distributed in an array and forming pixel driving circuit groups, each pixel driving circuit group includes pixel driving circuit rows with each including pixel driving circuits, each of which includes a driving circuit connected to a first, second and third nodes, to input a driving current to the third node through the second node in response to a signal of the first node; a first switching unit with a first end connected to a first power supply terminal and second end connected to the second node, to connect the first power supply terminal and the second node in response to a pulse width modulation signal; in a same pixel driving circuit group, a second end of any first switching unit is connected to a second end of at least one first switching unit in each of the other pixel driving circuit rows.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node; the first control circuit is configured to control a level of the second node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal; and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit includes a fifth transistor.

Abstract: A shift register, a gate drive circuit and a driving method therefor. The shift register includes a display pre-charge reset subcircuit, a sensing pre-charge reset subcircuit, a pull-down control subcircuit, an output subcircuit, a sensing cascade subcircuit and a black frame insertion cascade subcircuit. The display pre-charge reset subcircuit is configured to provide a signal of a first power supply end for a pull-up node under control of a first signal input end and provide a signal of a second power supply end to the pull-up node under control of a reset signal end; the sensing pre-charge reset subcircuit is configured to provide a signal of a first clock signal end to the pull-up node under control of the sensing cascade node and the first clock signal end, and provide a signal of the second power supply end to the pull-up node under control of a total reset end.

Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate includes: a base substrate including a special-shaped display area and a frame area located on one side of the special-shaped display area; and the special-shaped display area includes a first display area and a second display area on located on one side of the first display area, and the second display area is arranged in contact with the frame area; a group of data lines located on the base substrate and located in the first display area and the second display area; a group of fan-out lines located on a side of a layer where the group of data lines are located away from the base substrate, located in the first display area, and electrically connected to the data lines; and a group of dummy leads.

Abstract: Disclosed are a display substrate and a preparation method therefor, and a display apparatus. The display substrate includes a plurality of sub-pixels, wherein at least one sub-pixel includes a pixel drive circuit, the pixel drive circuit is respectively connected with a scan signal line (41, 42) and a first power supply line (60); and in at least one sub-pixel, the scan signal line (41, 42) is provided with at least one fracture (K1, K2), scan signal lines (41, 42) on both sides of the fracture (K1, K2) are connected with each other through a signal connection electrode (91, 92), a length of the signal connection electrode (91, 92) is larger than a width of the first power supply line (60), and the length of the signal connection electrode (91, 92) is smaller than a width of the sub-pixel.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output an output blanking output control signal; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal; a selection sub-circuit, having a first terminal connected to the second input sub-circuit, a second terminal connected to the first input sub-circuit, and a third terminal connected to a first node, configured to control a potential of the first node according to the display output control signal and the blanking output control signal; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node.

Abstract: Provided is a display panel. The display panel includes: a substrate; a plurality of first control lines and a plurality of second control lines on a side of the substrate; and a plurality of subpixels arranged in an array on the side of the substrate, wherein at least two of the plurality of subpixels share a first node; wherein the subpixel includes a first circuit and a second circuit, the first circuit and the second circuit being configured to control a voltage at the first node in response to a first control signal and a second control signal; wherein in the display panel, a sum of a number of the plurality of first control lines and a number of the plurality of second control lines is less than or equal to a number of the subpixels in a column direction.

Abstract: A shift register includes a first scan unit including a first input circuit and a first output circuit, and a second scan unit including a second input circuit, a second output circuit, and a potential boost circuit. The first input circuit is configured to transmit an input signal to a first pull-up node. The first output circuit is configured to, under a control of a voltage of the first pull-up node, output a shift signal and a first scan signal. The second input circuit is configured to transmit the input signal to a second pull-up node. The second output circuit is configured to output a second scan signal under a control of a voltage of the second pull-up node. The potential boost circuit is configured to boost the voltage of the second pull-up node in cooperation with the second output circuit.

Abstract: A transparent OLED display panel, a manufacturing method therefor, and a display apparatus are provided, relating to the field of display technologies. The display panel has a plurality of transparent regions and a plurality of display regions, wherein the transparent regions and the display regions are alternately arranged in a first direction. The display panel includes a plurality of pixels arranged in a second direction and a plurality of data lines; each of the pixels includes a plurality of sub-pixels, and the sub-pixels in each display region include a row of first sub-pixels and a row of second sub-pixels both arranged in the second direction; and the pixel at least includes one first sub-pixel and one second sub-pixel adjacent to each other. In the same display region, one first sub-pixel and one second sub-pixel adjacent to each other in the first direction are connected to the same data line.

Abstract: A shift register circuit includes an input sub-circuit, an output sub-circuit and a control sub-circuit. The input sub-circuit is coupled to a first input signal terminal and a pull-up node, and configured to, under control of a first input signal, transmit the first input signal to the pull-up node. The output sub-circuit is at least coupled to the pull-up node, a first clock signal terminal and a first signal output terminal, and configured to transmit a first clock signal to the first signal output terminal under control of a voltage at the pull-up node. The control sub-circuit is coupled to at least one first reference node, at least one first control signal terminal and the pull-up node, and configured to transmit a voltage at a first reference node to the pull-up node under control of a first control signal.

Abstract: An array substrate is provided. The array substrate includes a plurality of subpixels and a plurality of detection line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each of the plurality of detection line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, one detection line structure is provided between the (n)th row and (n+1)th row of subpixels in each subpixel row group, and the detection line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.

Abstract: An array substrate and a testing method thereof are provided. The array substrate includes a gate driving circuit, a plurality of clock signal lines and a plurality of testing terminals, wherein a number of the clock signal lines is greater than a number of the testing terminals; the plurality of clock signal lines are connected to the gate driving circuit and the plurality of testing terminals, and at least two clock signal lines are connected to a same testing terminal; and the plurality of testing terminals are configured to connect to a testing device.

Abstract: A display panel includes a plurality of sub-pixels, a sub-pixel includes a pixel driving circuit, and the pixel driving circuit includes at least a driving transistor and a storage capacitor. The display panel further includes a substrate, and a first gate conductive layer, a semiconductor layer and a second gate conductive layer that are disposed on the substrate. The first gate conductive layer includes a first electrode plate of the storage capacitor. The semiconductor layer includes an active layer pattern of the driving transistor. At least part of the active layer pattern of the driving transistor and at least part of the first electrode plate are disposed in a same layer. The second gate conductive layer includes a second electrode plate of the storage capacitor and a gate electrode of a driving transistor electrically connected to the second electrode plate.

Abstract: An array substrate and a display device are provided. The array substrate includes a base substrate, and gate lines, a gate driving structure, an interconnecting structure and an insulating layer. The gate lines are electrically connected with the gate driving structure through the interconnecting structure; the insulating layer is located between the gate lines and the interconnecting structure, and includes a first via hole and a second via hole. The gate line includes a first connecting portion and a second connecting portion, and the second connecting portion is located between the gate driving structure and the first connecting portion; the first connecting portion is electrically connected with the interconnecting structure through the first via hole, and a straight line extending in a direction perpendicular to the base substrate passes through the second connecting portion, the second via hole and the interconnecting structure in turn.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node; the first control circuit is configured to control a level of the second node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal; and the second output circuit is configured to output a second output signal at the second output terminal under control of the level of the second node.