Patents by Inventor Yongqian Li

Yongqian Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11424294
    Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array which includes N rows and 4M columns, sub-pixel units in each row is divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit and a fourth sub-pixel unit which are sequentially in four adjacent columns along a first direction.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 23, 2022
    Assignees: HEFEI BOE JOINT TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Can Yuan, Yongqian Li, Zhidong Yuan
  • Publication number: 20220262886
    Abstract: Provided are a display substrate and a preparation method therefor, and a display apparatus, which can not only avoid jumpers generated when a light-emitting device in a sub-pixel is electrically connected to a storage capacitor, in order to avoid the risk of crosstalk, but can also increase the pixel aperture ratio of the display substrate and increase the capacitance of the storage capacitor in a pixel driving circuit.
    Type: Application
    Filed: November 6, 2020
    Publication date: August 18, 2022
    Applicants: Hefei BOE Joint Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Can YUAN, Yongqian LI, Zhidong YUAN, Meng LI, Xuelian CHENG
  • Publication number: 20220262890
    Abstract: A display substrate includes: a base; a cathode power line disposed on the base and located in the peripheral region; a first insulating layer located on a side of a layer in which the cathode power line is located away from the base and having first via hole(s); a cathode layer located on the first insulating layer and electrically connected to the cathode power line through the first via hole(s); and spacer(s) located on a side of the cathode layer proximate to the base, a spacer covering at least a side wall of a first via hole, a thickness of a portion of the spacer covering the side wall decreasing along the side wall and in a direction pointing from an end of the side wall proximate to the base toward an end of the side wall of the first via hole away from the base.
    Type: Application
    Filed: February 9, 2021
    Publication date: August 18, 2022
    Applicants: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Leilei CHENG, Yongqian LI, Dacheng ZHANG
  • Publication number: 20220262315
    Abstract: A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node; the first input circuit includes a first transistor and a first capacitor, and a second electrode of the first capacitor is connected to the first electrode of the first transistor.
    Type: Application
    Filed: May 3, 2022
    Publication date: August 18, 2022
    Inventors: Xuehuan Feng, Yongqian Li
  • Publication number: 20220254311
    Abstract: The present disclosure provides a shift register unit, including a detection signal input sub-circuit, a display signal input sub-circuit, an output circuit, a pull-down control circuit and a signal output terminal, the output circuit includes a pull-up sub-circuit and a pull-down sub-circuit, the pull-down control circuit includes a selection sub-circuit and a plurality of pull-down control sub-circuits. The present disclosure further provides a gate driving circuit, a display panel and a driving method for driving the display panel. The shift register unit has a simple structure and a long service life.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Inventors: Xuehuan FENG, Yongqian LI
  • Patent number: 11410608
    Abstract: Embodiments of the present disclosure provide a shift register circuitry, a gate driving circuit, a display device, and a driving method. The shift register circuitry includes a blanking input circuit, a display input circuit, an output circuit, and a first control circuit. The blanking input circuit provides a blanking input signal to the pull-up control node and supplies a blanking pull-up signal to the pull-up node. The display input circuit provides a display pull-up signal to the pull-up node in response to the display input signal. The output circuit outputs the output signal to the shift signal output terminal and the pixel signal output terminal under the control of the voltage of the pull-up node. The first control circuit couples the shift signal output terminal to the pixel signal output terminal in response to the display input signal.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: August 9, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xuehuan Feng, Yongqian Li, Can Yuan
  • Patent number: 11410597
    Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 9, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xuehuan Feng, Yongqian Li
  • Patent number: 11403990
    Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit. The blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node. The first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: August 2, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xuehuan Feng, Yongqian Li
  • Publication number: 20220238062
    Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 28, 2022
    Applicants: Hefei BOE Joint Technology Co.,Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xuehuan Feng, Yongqian Li, Xing Zhang
  • Publication number: 20220238055
    Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes a first input circuit, an output control circuit, and an output circuit. The first input circuit is configured to output a first input signal to a first node in response to a first control signal; the output control circuit is configured to output an output control signal to a second node under control of a level of the first node; and the output circuit includes an output terminal, and the output circuit is configured to output an output signal to the output terminal under control of a level of the second node.
    Type: Application
    Filed: April 15, 2022
    Publication date: July 28, 2022
    Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xuehuan Feng, Yongqian Li
  • Patent number: 11398179
    Abstract: A shift register unit, a gate drive circuit, a display device and a driving method are provided. The shift register unit includes a sub-shift register, a second sub-shift register and an output control circuit. The first sub-shift register includes a first output terminal and a first control node, and is configured to output a first clock signal under control of a level of the first control node. The second sub-shift register include a second output terminal and a second control node, and the second output terminal outputs a display output signal in a display phase and a random output signal in a blank phase under control of a level of the second control node. The output control circuit is connected to the first sub-shift register and the second control node, and is configured to control the level of the second control node under control of an output control signal.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: July 26, 2022
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Zhidong Yuan, Yongqian Li, Xuehuan Feng, Can Yuan
  • Patent number: 11393405
    Abstract: Provided are a shift register unit circuit and drive method, and a gate driver and a display device. The shift register unit circuit includes a first sub-unit circuit, a second sub-unit circuit, a third sub-unit circuit, and a fourth sub-unit circuit. Responsive to providing a corresponding input pulse and clock signal, the shift register unit circuit is configured output first, second, third, and fourth output signals. The shift register unit circuit is configured such that a fifth node is in conduction with a second node at least while the reset pulse is active.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: July 19, 2022
    Assignees: HEFEI BOE JOINT TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xuehuan Feng, Yongqian Li
  • Patent number: 11393402
    Abstract: An OR logic operation circuit and a driving method, a shift register unit, a gate drive circuit, and a display device are provided. The OR logic operation circuit includes: a first inverter, a second inverter, a first control circuit, and a second control circuit. The first inverter is configured to invert a first control signal, which is received, to output a second control signal; the second inverter is configured to invert a third control signal received to output a fourth control signal; the first control circuit is configured to perform first control on a first node and the output terminal to achieve an OR operation and output a first level of an output signal at the output terminal; and the second control circuit is configured to perform second control on the first node and the output terminal to output a second level of the output signal at the output terminal.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: July 19, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhidong Yuan, Yongqian Li, Can Yuan, Meng Li
  • Patent number: 11393385
    Abstract: A shift register includes a first reset circuit having a first transistor and a second transistor, and a selection control circuit connected to a pull-down node, and control electrodes of the first and second transistors. First electrodes of the first and second transistors are connected to a first voltage terminal, and second electrodes of the first and second transistors are connected to a signal output terminal. The selection control circuit is configured to: control a line between the pull-down node and the control electrode of the first transistor, and a line between the pull-down node and the control electrode of the second transistor to be alternately closed. The first reset circuit is configured to output a voltage of the first voltage terminal to the signal output terminal under control of a potential at the pull-down node transmitted by the selection control circuit.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: July 19, 2022
    Assignees: Hefei BOE Joint Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xuehuan Feng, Yongqian Li
  • Publication number: 20220223096
    Abstract: A shift register circuit includes:an input sub-circuit connected to a first node, and configured to receive a first control signal, and cause a potential of the first node to jump from an initial potential to a first potential greater than the initial potential; an output sub-circuit connected to the first node, and configured to receive a first clock signal, generate an output signal, cause the potential of the first node to jump from the first potential to a third potential greater than the first potential; and a chamfering sub-circuit connected to the first node, and configured to receive a second control signal, cause the potential of the first node to gradually decrease from the third potential to a fourth potential greater than the initial potential and less than the third potential, and cause the potential of the first node to jump from the fourth potential to the initial potential.
    Type: Application
    Filed: September 28, 2020
    Publication date: July 14, 2022
    Inventors: Xuehuan FENG, Yongqian LI
  • Publication number: 20220208948
    Abstract: A display substrate has a display area including a plurality of sub-display areas. The display substrate includes a base, a plurality of columns of pixels, a plurality of first and second power lines disposed on the base. At least two columns of pixels are disposed in each sub-display area, and each column of pixels includes at least three columns of sub-pixels. At least one first power line is disposed in each sub-display area and configured to provide a first power signal to all sub-pixels in a sub-display area. The second power lines are configured to provide second power signals to all sub-pixels. A plurality of columns of sub-pixels are disposed between any two adjacent power lines, to and any first and second power lines are each arranged between two adjacent columns of sub-pixels emitting light of a first color and sub-pixels emitting light of a second color.
    Type: Application
    Filed: November 17, 2020
    Publication date: June 30, 2022
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Pan XU, Yongqian LI, Dacheng ZHANG, Lang LIU
  • Patent number: 11373577
    Abstract: The present application discloses a shift-register unit. The shift-register unit includes a first sub-unit including a first input circuit coupled via a first node to a first output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal and the first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. Additionally, the shift-register unit includes a second sub-unit including a second input circuit coupled via a second node to a second output circuit. The second input circuit is configured to control a voltage level of the second node in response to the first input signal and the second output circuit is configured to output a second output signal in response to the voltage level of the second node.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: June 28, 2022
    Assignees: Hefei BOE Joint Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xuehuan Feng, Yongqian Li, Xing Zhang
  • Publication number: 20220189406
    Abstract: The present disclosure provides a shift register unit, a gate driving circuitry and a method for driving the gate driving circuitry. The shift register unit includes an input circuitry, a first latch circuitry, a second latch circuitry and an output end. The input circuitry is configured to output an input control signal to the first latch circuitry in accordance with a first level signal, a second level signal and a first ON signal. The first latch circuitry is configured to output an output signal as a gate driving signal via the output end in accordance with a first clock signal and the input control signal, and latch the output signal. The second latch circuitry is configured to output a second ON signal in accordance with a second clock signal and the output signal, and latch the second ON signal.
    Type: Application
    Filed: June 20, 2021
    Publication date: June 16, 2022
    Inventors: Xuehuan FENG, Yongqian LI, Pan XU
  • Patent number: 11361715
    Abstract: The present disclosure provides a shift register unit, a gate driving circuitry and a method for driving the gate driving circuitry. The shift register unit includes an input circuitry, a first latch circuitry, a second latch circuitry and an output end. The input circuitry is configured to output an input control signal to the first latch circuitry in accordance with a first level signal, a second level signal and a first ON signal. The first latch circuitry is configured to output an output signal as a gate driving signal via the output end in accordance with a first clock signal and the input control signal, and latch the output signal. The second latch circuitry is configured to output a second ON signal in accordance with a second clock signal and the output signal, and latch the second ON signal.
    Type: Grant
    Filed: June 20, 2021
    Date of Patent: June 14, 2022
    Assignees: Hefei BOE Joint Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xuehuan Feng, Yongqian Li, Pan Xu
  • Patent number: 11361696
    Abstract: A shift register includes an output sub-circuit, a cascade sub-circuit and at least one additional output sub-circuit. The output sub-circuit is configured to transmit a first clock signal received at the first clock signal terminal to the output signal terminal under control of a potential at the pull-up node, so as to scan a gate line coupled to the output signal terminal. The cascade sub-circuit is configured to transmit a second clock signal received at the second clock signal terminal to the cascade node under the control of the potential at the pull-up node. Each additional output sub-circuit is configured to transmit a clock signal received at a corresponding clock signal terminal to a corresponding additional output signal terminal under control of a potential at the cascade node, so as to scan a gate line coupled to the corresponding additional output signal terminal.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 14, 2022
    Assignees: HEFEI BOE JOINT TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xuehuan Feng, Yongqian Li