Abstract: A display panel and a display device are provided, since a plurality of source ICs (01) are arranged, a large-sized display panel is driven, and since the plurality of source ICs (01) are scattered around a display area (A) along the tangential directions of the edge of the display area (A), that is, the source ICs (01) are distributed according to the shape of the display panel, a distance between the source ICs (01) and the display area (A) is shortened, and thus a narrow bezel design of the display panel is facilitated.

Abstract: Disclosed are a display substrate and a display device. A display region and a peripheral region are included. The peripheral region includes a plurality of shift registers and a plurality of clock signal lines. The plurality of clock signal lines are arranged side by side in a first direction and include a first clock signal line to a Zth clock signal line, Z?1. The shift registers are connected with gate lines in the display region and the first clock signal line to the Zth clock signal line respectively. There is at least a group of ith clock signal lines satisfying that the ith clock signal lines include X ith clock signal lines which are arranged one by one according to a sequence of connection with shift registers and further include N ith clock signal lines.

Abstract: A pixel circuit, a driving method of pixel circuit, and a display device are provided. The pixel circuit includes: a light emitting device, a driving sub-circuit, an energy storage sub-circuit, a data writing sub-circuit and a pull-down sub-circuit; the data writing sub-circuit is configured to control a voltage signal on a data line to be written into a control end of the driving sub-circuit in response to a data writing control signal; a first end of the driving sub-circuit is electrically connected to a target node, a second end of the driving sub-circuit is electrically connected to a power supply voltage, and the driving sub-circuit is configured to control a conduction of the driving sub-circuit under a control of a voltage on a control end of the driving sub-circuit.

Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes a base substrate, a plurality of pixel units and a plurality of gate line groups. At least one pixel unit includes a plurality of sub-pixels. At least one sub-pixel includes a sensing transistor and a driving transistor. Each gate line group includes a first gate line and a second gate line; for the first gate line and the second gate line corresponding to the sub-pixels in the same row, the positions of the sensing transistors are closer to the second gate lines, and the positions of the driving transistors are closer to the first gate line, For two sub-pixels close to each other and located in different pixel units in the same row, at least one signal line has a double-layer alignment structure, and the double-layer alignments are electrically connected with each other.

Abstract: A display panel includes a plurality of rows of sub-pixels and at least one gate driver circuit that are disposed on a base substrate. Each sub-pixel includes a pixel driver circuit and a light-emitting device coupled to the pixel driver circuit, and a gate driver circuit includes a plurality of shift registers that are cascaded and a plurality of control signal lines. A shift register is coupled to a plurality of pixel driver circuits in at least one row of sub-pixels and at least a part of the plurality of control signal lines, and includes a plurality of first thin film transistors that are divided into a plurality of first thin film transistors. At least one thin film transistor group is located in the display region and distributed between adjacent sub-pixels in a same row of sub-pixels.

Abstract: A shift register a first scan unit a leakage prevention unit, and a leakage input unit. The first scan unit includes a first input circuit configured to transmit an input signal to a first pull-up node. The leakage prevention input unit is configured to: in response to a first voltage signal received at a first voltage signal terminal, transmit a the first voltage signal to a leakage prevention input node and in response to a second voltage signal received at a second voltage signal terminal, to transmit the second voltage signal to the leakage prevention input node (M) in The first voltage signal and the second voltage signal are mutually inverted signals. The leakage prevention unit is configured to transmit one of the first voltage signal and the second voltage signal from the leakage prevention input node to a first leakage prevention node.

Abstract: A shift register comprises a first shift register unit and a second shift register unit. The first shift register unit comprises a first input circuit connected to a first input terminal and a first pull-up node, a first output circuit connected to the first pull-up node, a first output terminal and a first clock terminal, a first pull-down circuit and a unidirectional isolation circuit, and the first output terminal is connected to the first pull-down circuit by the unidirectional isolation circuit. The second shift register unit comprises a second input circuit connected to a second input terminal and a second pull-up node, and a second output circuit connected to the second pull-up node, a second output terminal and a second clock signal, and the second output terminal is connected to a node between the first pull-down circuit and the unidirectional isolation circuit.

Abstract: A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node; the first input circuit includes a first transistor and a first capacitor, and a second electrode of the first capacitor is connected to the first electrode of the first transistor.

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes a base substrate and a scan line, a data line, a power supply line, a sensing line, a pixel driving circuit and a light-emitting unit that are sequentially stacked on the base substrate. The array substrate also includes a gate layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first electrode of the storage capacitor is at least disposed at the first conductive layer, and the second electrode of the storage capacitor is at least disposed at the second conductive layer. The data line, the power supply line, and the sensing line are disposed at the third conductive layer.

Abstract: The present disclosure provides an array substrate, a display panel, a display device and a manufacturing method, for solving the problems in the prior art that the array substrate is larger in number of circuits, the area needed for punching is larger, and the high pixel resolution cannot be achieved easily.

Abstract: A display substrate includes: a base substrate; a first conductive pattern arranged on the base substrate; a first insulation layer arranged at a side of the first conductive pattern away from the base substrate; a second conductive pattern arranged at a side of the first insulation layer away from the base substrate; a second insulation layer arranged at a side of the second conductive pattern away from the base substrate; and a third conductive pattern arranged at a side of the second insulation layer away from the base substrate. The third conductive pattern and the first conductive pattern together serve as a first electrode plate of the capacitor, and the second conductive pattern serves as a second electrode plate of the capacitor.

Abstract: A display panel includes a substrate, a pad, an auxiliary electrode layer, a data line layer, a first electrode layer, a light emitting layer, and a second electrode layer. The substrate has a display area and a peripheral area. The pad is disposed on a side of the substrate and located in the peripheral area. The auxiliary electrode layer is disposed on the same side of the substrate as the pad; the data line layer is disposed on a same layer as the auxiliary electrode layer; the first electrode layer is disposed on a side of the auxiliary electrode layer facing away from the substrate; the light emitting layer is disposed on a side of the first electrode layer facing away from the substrate; and the second electrode layer is disposed on a side of the light emitting layer facing away from the substrate and connected to the auxiliary electrode layer.

Abstract: The invention provides a shift register, a drive method thereof, a gate drive circuit, and a display panel. Wherein, the shift register comprises: a display control circuit connected to a pull-up node, a first power terminal and a first control terminal; a sensing control circuit connected to the pull-up node, a second control terminal and a third control terminal and configured to store a potential of the pull-up node in a display mode under the control of the second control terminal and write the stored potential into the pull-up node in a sensing mode under the control of the third control terminal; and a first output circuit connected to the pull-up node, a first clock terminal and a first output terminal.

Abstract: The disclosure provides a shift register, a drive method thereof, a gate drive circuit, and a display panel. The shift register comprises a first shift register unit and a second shift register unit.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the same, a driving method and a display device. The display substrate includes a base substrate, gate lines, data lines and sub-pixels. The sub-pixels include sub-pixel columns corresponding to the data lines in a one-to-one manner. In a sub-pixel driving circuit of the sub-pixel, a driving transistor and a data writing transistor are located at a first side of an aperture area of the sub-pixel; a sensing transistor is located at a second side of the aperture area of the sub-pixel. The first side and the second side are opposite sides of the aperture area along the extension direction of the data lines. Gate electrodes of sensing transistors in a same sub-pixel row, and gate electrodes of data writing transistors in an adjacent next sub-pixel row, are all coupled to a gate line corresponding to the adjacent next sub-pixel row.

Abstract: Disclosed are an apparatus and a method for granulation of a blast furnace slag and recycling of waste heat. The apparatus comprises an aerosol granulation nozzle module, a flow guide, a cyclone separator and a waste heat recovery device; wherein the aerosol granulation nozzle module comprises a slag flow controller, a compressed air flow control valve, a water volume control valve and an aerosol spray gun; the flow guide is configured to fully mix the medium temperature gas and the high-temperature granular slag having a primarily solidified surface in the flow guide; and the cyclone separator is configured to separate the high-temperature granular slag and the medium-to-high-temperature gas. The present invention completes the granulation of blast furnace slag, and organically couples slag sensible heat recovery with sludge drying, thereby recovering the waste heat in the process of slag granulation and improving the efficiency of waste heat recovery and utilization.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, and a leakage prevention circuit. The first sub-circuit includes a first input circuit and a first output circuit, the first input circuit is configured to control a level of a first node in response to a first input signal. The second sub-circuit includes a second input circuit and the second output circuit. The leakage prevention circuit is connected to the first node, and is configured to control a level of the leakage prevention node under control of the level of the first node, so that a circuit connected between the first node and the leakage prevention node is turned off, and a circuit connected between the second node and the leakage prevention node is turned off.

Abstract: This application relates to display panels, methods of driving the same, and display devices. The display panel includes: a first pixel circuit and a demultiplexing circuit. The first pixel circuit includes a first reset circuit, a first data writing circuit, and a first drive circuit. A first terminal of the first reset circuit is connected to a first terminal of the first drive circuit. A second terminal of the first reset circuit is connected to a first multiplexing signal line. A control terminal of the first drive circuit is connected to a first terminal of the first data writing circuit. A second terminal of the first data writing circuit is connected to the first multiplexing signal line. The demultiplexing circuit includes a first control circuit and a second control circuit. A first terminal of the first control circuit is connected to the first multiplexing signal line. A second terminal of the first control circuit is used for receiving a reset signal.

Abstract: A method for compensating display brightness, a circuit for compensating display brightness, and a display device are provided. The method for compensating display brightness is applicable to a display device. A first group of sub-pixel rows in the display device perform normal display and black frame insertion display in a same frame display period. A second group of sub-pixel rows in the display device perform normal display in a current frame display period and an adjacent next frame display period, and perform black insertion display in the adjacent next frame display period. A first interval period is provided between the current frame display period and the adjacent next frame display period. The method for compensating includes: compensating luminous brightness of the first group of sub-pixel rows and/or compensating luminous brightness of the second group of sub-pixel rows.

Abstract: A multiplexer circuit includes a first selection sub-circuit and a second selection sub-circuit. The first selection sub-circuit configured to transmit an input signal received at a input signal terminal to a first output terminal in response to a first control signal received at a first control terminal, and transmit a voltage of a power supply voltage terminal to the first output terminal in response to a second control signal received at a second control terminal. The second selection sub-circuit configured to transmit the input signal received at the input signal terminal to a second output terminal in response to a third control signal received at a third control terminal, and transmit the voltage of the power supply voltage terminal to the second output terminal in response to a fourth control signal received at a fourth control terminal.