Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array, and the array includes N rows and 8M columns. Sub-pixel units in each row are divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit, a fourth sub-pixel unit, a fifth sub-pixel unit, a sixth sub-pixel unit, a seventh sub-pixel unit and an eighth sub-pixel unit which are sequentially in eight adjacent columns along a first direction.

Abstract: A display substrate, manufacturing method thereof, and display device. The display substrate comprises: a substrate, gate line, data line, power connection line and multiple sub-pixels on the substrate, the display substrate has defective points formed by short-circuiting of the gate line and data line, and the gate line forming defective points is a defective gate line; the data line forming defective points is a defective data line; the power connection line is arranged on the same layer as gate electrodes of multiple transistors; the defective gate line and defective power connection line are disconnected, the display substrate further comprises: a repair line disposed on one side, away from the substrate, of the source drain electrode of multiple transistors, the repair line is respectively connected to the partially disconnected defective gate line and partially disconnected defective power connection line, and is used for transmitting scanning signals to repair the display substrate.

Abstract: The disclosure provides a shift register, a drive method thereof, a gate drive circuit, and a display panel. The shift register comprises a first shift register unit and a second shift register unit.

Abstract: Embodiments of the present disclosure provide a shift register. The shift register includes a blank input circuit, N shift register circuits, and a compensation selection circuit. The blank input circuit is configured to store a blank input signal, and provide a blank pull-down signal to N pull-down nodes based on the blank input signal and a blank control signal. The N shift register circuits are respectively coupled to the blank input circuit via the N pull-down nodes, and are configured to output respective blank output signals based on the blank pull-down signal and respective clock signals during a blank period. The compensation selection circuit is configured to provide the blank input signal to the blank input circuit under the control of a compensation selection control signal. Herein N is a natural number greater than 1.

Abstract: A pixel circuit includes: a first driving line, a second driving line, a data line, and a sensing line; a first pixel sub-circuit including a first writing unit, a first sensing unit, and a first driving unit, the first driving unit being configured to drive a first light-emitting unit to emit light; and a second pixel sub-circuit including a second writing unit, a second sensing unit, and a second driving unit, the second driving unit being configured to drive a second light-emitting unit to emit light. The first writing unit and the second sensing unit are connected to the first driving line, so as to be turned on or off synchronously under control of the first driving line. The second writing unit and the first sensing unit are connected to the second driving line, so as to be turned on or off synchronously under control of the second driving line.

Abstract: A shift register unit and a method of driving the shift register unit, a gate driving circuit, and a display device. The shift register unit includes: a first shift register configured to generate a first control output signal (CR1) and a second control output signal (CR2) based on a signal at a first clock signal terminal (CLKD); and a second shift register configured to generate a second output signal (OUT2) based on a signal at a third clock signal terminal (CLKE2), wherein a first pull-down node (PD1_1) of the first shift register is connected to second pull-down node (PD2_2) of the second shift register, and a second pull-down node (PD1_2) of the first shift register is connected to first pull-down node (PD2_1) of the second shift register.

Abstract: A pixel unit includes a first sub-pixel circuit and a second sub-pixel circuit. The first sub-pixel circuit includes a first sub-pixel driving circuit and a first light-emitting element, and the second sub-pixel circuit includes a second sub-pixel driving circuit and a second light-emitting element. The first sub-pixel driving circuit and the second sub-pixel driving circuit are connected to a first data line, and the first sub-pixel driving circuit is connected to a first gate line, the second sub-pixel driving circuit is connected to the second gate line. The first sub-pixel driving circuit is configured to drive the first light-emitting element by a data voltage on the first data line under the control of the first gate line. The second sub-pixel driving circuit is configured to drive the second light-emitting element by the data voltage on the first data line under the control of the second gate line.

Abstract: The present disclosure relates to a gate drive circuit. The gate drive circuit includes: cascaded GOA units, first clock signal lines, second clock signal lines, connecting lines and electrostatic protection sub-circuits. The first clock signal lines are used to provide various clock signals to the GOA units. The second clock signal lines are used to, when any of the clock signal lines is broken, replace the broken clock signal line to transmit a corresponding clock signal. The electrostatic protection sub-circuits are electrically connected to corresponding first clock signal lines or corresponding second clock signal lines through the connecting lines. Orthographic projections of the connecting lines on a plane where corresponding first clock signal lines or corresponding second clock signal lines are located intersect with the corresponding first clock signal lines and the corresponding second clock signal lines, respectively.

Abstract: A shift register unit and a drive method thereof, a gate drive circuit, and a display device are provided. A shift register unit includes a first noise reduction circuit, a first input circuit, and an output circuit; the first input circuit is coupled to a first node, and is configured to input a first control signal to the first node in response to a first input signal; the output circuit is coupled to the first node and an output terminal, and is configured to output a first output signal to the output terminal under control of a level of the first node; and the first noise reduction circuit is coupled to the output terminal, and is configured to perform noise reduction on the output terminal in response to a level of the output terminal.

Abstract: The present disclosure discloses a shift register and a driving method therefor, a gate drive circuit, and a display device. An input circuit is configured to respond to a signal of an input signal end and provide a signal of a first reference signal terminal to a first node; a reset circuit is configured to respond to the signal of the second node and provide a signal of a second reference signal end to the first node; and an output circuit is configured to respond to the signal of the first node and provide the signal of the clock signal end to an output signal end and is configured to respond to the signal of the third node and provide the signal of the second reference signal end to the output signal end.

Abstract: A shift register unit, a grid drive circuit, a display device and a driving method are disclosed. The shift register unit includes a display sub-shift-register and a detection sub-shift-register. The display sub-shift-register includes a display output terminal, and the display sub-shift-register is configured to output a display output signal of the shift register unit from the display output terminal at a display stage; the detection sub-shift-register is connected to a display output terminal of the display sub-shift-register to receive a display output signal, and includes a first random pulse signal terminal to receive a first random pulse signal. The detection sub-shift-register is configured to output a detection output signal of the shift register unit when the display output signal is at a turn-on level and the first random pulse signal is at a turn-on level.

Abstract: A shift register unit and a driving method thereof, a gate driving circuit, and a display device are provided. A shift register unit includes a blanking input circuit, a display input circuit, an output circuit; the blanking input circuit is configured to input a blanking control signal to a first node during a blanking period in response to a blanking input signal, the blanking input circuit includes a charging sub-circuit, the charging sub-circuit is configured to input the blanking control signal to a control node in response to a first compensation control signal and a second compensation control signal, the display input circuit is configured to input a display control signal to the first node during a display period in response to a display input signal; the output circuit is configured to output a composite output signal to an output end under control of a level of the first node.

Abstract: A shift register is provided, which may include a compensation selection circuit, a holding circuit, and N shift register circuits. The hold circuit may hold a blanking input signal. Each of the shift register circuits may include a blanking input circuit and an output circuit. The blanking input circuit may provide a blanking pull-down signal to a first node according to the blanking input signal and a blanking control signal. The output circuit may output a shift signal via a shift signal output terminal and output a first drive signal via a first drive signal output terminal according to a voltage of the first node. The compensation selection circuit may provide, according to a compensation selection control signal and the shift signal from one of the N shift register circuits, the blanking input signal to the holding circuit and the N shift register circuits.

Abstract: A display panel, a display device, and a driving method of the display panel are provided. The display panel includes a plurality of pixel units arranged in an array and data lines and sensing lines connected to the pixel units, and each of the plurality of pixel units includes a plurality of sub-pixels; all sub-pixels in a same column of pixel units are connected to a same data line, each column of pixel units is respectively connected to two of the sensing lines, and any two adjacent columns of pixel units share one of the sensing line.

Abstract: A shift register circuit is provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a first control sub-circuit and a second control sub-circuit. The input sub-circuit is connected to a first signal input terminal, a second signal input terminal and a first node. The output sub-circuit is connected to the first node, a first clock signal terminal and a first output terminal. The first control sub-circuit is connected to a first power supply voltage terminal, a second power supply voltage terminal, the first node and a second node. The second control sub-circuit is connected to the second power supply voltage terminal, a third power supply voltage terminal, the second node and a third node, and the third node is further connected to the input sub-circuit.

Abstract: The present disclosure discloses a shift register, a driving method thereof, a gate drive circuit, an array substrate and a display device. With a signal control circuit, a branch control circuit, a cascade signal output circuit and at least two scan signal output circuits, each shift register can output at least two scan signals to correspond to different gate lines in a display panel. This can reduce the number of shift registers in a gate drive circuit and the space occupied by the gate drive circuit and can achieve an ultra-narrow frame design, as compared with an existing shift register that can only output one scan signal. Moreover, as signals of different output control node do not influence each other, the output stability can also be improved.

Abstract: A transparent OLED display panel, a manufacturing method therefor, and a display apparatus, relate to the field of display technologies. The transparent OLED display panel has a plurality of transparent regions (a) and a plurality of display regions (b), wherein the transparent regions and the display regions are alternately arranged (a) in a first direction. The transparent OLED display panel includes a plurality of pixels (1) arranged in a second direction and a plurality of data lines (31, 32) extending along the first direction; each of the pixels (1) includes a plurality of sub-pixels (11), and the sub-pixels (11) in each display region (b) include a row of first sub-pixels (111) and a row of second sub-pixels (112) both arranged in the second direction; and the pixel at least includes one first sub-pixel (111) and one second sub-pixel (112) adjacent to each other in the first direction.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit. The input circuit is configured to control a level of a first node in response to an input signal input; the first control circuit is configured to control a level of the second node in response to the input signal and the level of the first node; the blanking control circuit is configured to control the level of the first node and the level of the second node; the first output circuit is configured to output a first output signal at the first output terminal; and the second output circuit is configured to output a second output signal at the second output terminal.

Abstract: A shift register unit, a gate driving circuit, a display device, and a method for controlling a shift register unit are provided. The shift register unit includes a first input sub-circuit, a second input sub-circuit, a first isolation sub-circuit, and a first output sub-circuit. The first input sub-circuit is configured to control a potential of a first node. The second input sub-circuit is configured to control a potential of a second node. The first isolation sub-circuit is configured to control conduction and interruption of electrical coupling between the first node and the second node. The first output sub-circuit is configured to output a grate driving signal in a display phase and output a compensation driving signal in a field blanking phase.

Abstract: A display panel, a display device and a control method for a display panel are provided. The display panel comprises a plurality of pixel circuits, each of which includes a driving transistor, an energy storage unit, a data writing unit, a reset unit, a compensation unit, and a light emitting unit. The display panel further comprises a driving circuit, which is used to control the compensation unit during a compensation period so as to disconnect the other terminal of the energy storage unit from one terminal of the light emitting unit, so that the light emitting unit in each of the pixel circuits is in an extinguished state.