Abstract: A shift register unit, a gate driving circuit, a display device, and a method for controlling a shift register unit are provided. The shift register unit includes a first input sub-circuit, a second input sub-circuit, a first isolation sub-circuit, and a first output sub-circuit. The first input sub-circuit is configured to control a potential of a first node. The second input sub-circuit is configured to control a potential of a second node. The first isolation sub-circuit is configured to control conduction and interruption of electrical coupling between the first node and the second node. The first output sub-circuit is configured to output a grate driving signal in a display phase and output a compensation driving signal in a field blanking phase.

Abstract: A display panel, a display device and a control method for a display panel are provided. The display panel comprises a plurality of pixel circuits, each of which includes a driving transistor, an energy storage unit, a data writing unit, a reset unit, a compensation unit, and a light emitting unit. The display panel further comprises a driving circuit, which is used to control the compensation unit during a compensation period so as to disconnect the other terminal of the energy storage unit from one terminal of the light emitting unit, so that the light emitting unit in each of the pixel circuits is in an extinguished state.

Abstract: A shift register unit, a gate driving circuit, a display device and a driving method. The shift register unit includes a blank input circuit, a blank pull-up circuit, a display input circuit, and an output circuit. The blank input circuit charges and holds the level of the pull-up control node, the blank pull-up circuit uses a first clock signal to charge a pull-up node, the display input circuit charges the pull-up node, and the output circuit outputs a plurality of output clock signals respectively to a plurality of output terminals. The plurality of output terminals include a shift signal output terminal and a plurality of pixel signal output terminals. The plurality of pixel signal output terminals are configured to respectively output a plurality of pixel signals to a plurality of rows of pixel units.

Abstract: The present disclosure discloses an array substrate and a driving method thereof, a display panel and a display device. The array substrate comprises: a plurality of gate scanning lines extending in a first direction, a plurality of data lines extending in a second direction and detection signal lines, where the data lines and the gate scanning lines are crossed to define a plurality of pixel circuits arranged in an array. The pixel circuits comprise: first transistors, second transistors, driving transistors, capacitors, and light emitting devices, and in the same pixel circuit, the first transistor and the second transistor are electrically connected to different gate scanning lines.

Abstract: The present disclosure discloses a pixel driving circuit and a method of driving the same, a display panel and a display apparatus. The pixel driving circuit includes: a driving circuit, an energy storage circuit, a data and sensing line, a first initialization circuit, a second initialization circuit and a data writing circuit.

Abstract: Embodiments of the present disclosure provide an array substrate, a display device. The array substrate comprises first power lines and second power lines disposed on a substrate, wherein the first power line crosses the second power line to define a pixel region, wherein the first power lines crosses the second power lines at intersection points, and the intersection points include a first intersection point where the first power line is electrically connected to the second power line and a second intersection point where the first power line is insulated from the second power line are insulated; the first intersection points for each of the first power supply lines and/or the first intersection points for each of the second power supply lines are distributed at intervals.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-unit and a leakage prevention circuit; the first sub-unit includes a first input circuit and a first output circuit. The first input circuit controls a level of a first node in response to a first input signal, the first output circuit provides an output signal at an output terminal under control of the level of the first node, the leakage prevention circuit is connected to the first node and a first voltage terminal, and controls a level of a leakage prevention node under control of the level of the first node, whereby a conductive path is formed between the leakage prevention node and the first voltage terminal, and a circuit connected between the first node and the leakage prevention node is turned off.

Abstract: The application provides a pixel driving method, a pixel driving device and a display device. The method includes steps of: obtaining a brightness sum of a frame according to a brightness of each of pixels in the frame; inquiring a data voltage compensation value corresponding to the obtained brightness sum from a preset first correspondence relationship, the first correspondence relationship including a one-to-one correspondence relationship between the brightness sum and the data voltage compensation value for one frame; compensating a data voltage of the frame according to the data voltage compensation value to generate a compensated data voltage; and outputting the compensated data voltage to a display panel.

Abstract: A shift register unit, a gate driving circuit, a display device and a driving method. The shift register unit includes a blank input circuit, a blank pull-up circuit, a display input circuit, and an output circuit. The blank input circuit charges and holds the level of the pull-up control node, the blank pull-up circuit uses a first clock signal to charge a pull-up node, the display input circuit charges the pull-up node, and the output circuit outputs a plurality of output clock signals respectively to a plurality of output terminals. The plurality of output terminals include a shift signal output terminal and a plurality of pixel signal output terminals. The plurality of pixel signal output terminals are configured to respectively output a plurality of pixel signals to a plurality of rows of pixel units.

Abstract: The embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, and a display device. The shift register includes a compensation selection circuit, a storage circuit, a blanking input circuit, and a shift register circuit. The compensation selection circuit is configured to provide an input signal to a first node. The storage circuit is configured to store and maintain a voltage difference between a blanking control signal terminal and the first node. The blanking input circuit is configured to provide a blanking input signal to a second node. The shift register circuit is configured to provide a compensation driving signal during a blanking period, and provide a scan driving signal during a display period.

Abstract: An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate, and a GOA circuit, a source electrode IC and PLG wires arranged on the base substrate, and the PLG wires connect the GOA circuit with the source electrode IC. The GOA circuit transmits a GOA signal, and the GOA signal comprises a cascade signal and a non-cascade signal. The PLG wires comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits the cascade signal, the second PLG wire group transmits the non-cascade signal, a line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located at a side of the second PLG wire group distal to an active area of the base substrate.

Abstract: A shift register unit and a driving method thereof, a gate driving circuit, and a display device. The shift register unit includes: an input circuit, a first capacitor circuit, an output circuit, an output pull-down circuit, a coupling circuit, and an inverter circuit. The inverter circuit is coupled to an input control terminal, a first node, a second node, and a first level signal input terminal, and a second level signal input terminal; and used to control to connect or disconnect the second node and the first level signal input under the control of the input control terminal and the first level signal input terminal; also used to control to connect or disconnect the second node and the second level signal input terminal under the control of the first node and the second level signal input terminal.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, and a leakage prevention circuit. The first sub-circuit includes a first input circuit and a first output circuit, the first input circuit is configured to control a level of a first node in response to a first input signal. The second sub-circuit includes a second input circuit and the second output circuit. The leakage prevention circuit is connected to the first node, and is configured to control a level of the leakage prevention node under control of the level of the first node, so that a circuit connected between the first node and the leakage prevention node is turned off, and a circuit connected between the second node and the leakage prevention node is turned off.

Abstract: A shift register unit, a driving method thereof, a gate driver and a display device are provided. The shift register unit includes a first input circuit, an output circuit and a charging enhancement circuit. The first input circuit is configured to charge a first node in response to a first input signal; the output circuit is configured to output, under control of a level of the first node, a shift signal for a row-by-row shift of scanning and a first output signal for driving one row of sub-pixel units in a display panel to perform display scanning; and the charging enhancement circuit is configured to further enhance the level, of the first node in response to a charging enhancement signal. The shift register unit may enhance the level of the first node and the reliability of the gate driver and the display device consisted of the shift register unit.

Abstract: An electronic panel, a display device, and a driving method are disclosed. In the electronic panel, each sub-pixel unit includes a light emitting unit, a pixel driving circuit for driving the light emitting unit to emit light, and a sensing circuit for sensing the pixel driving circuit; the gate driving circuit includes N+1 output terminals, and is configured to output gate scanning signals that turn on the N rows of the plurality of sub-pixel units row by row; the pixel driving circuits of the sub-pixel units in a j-th row are connected to a j-th output terminal of the gate driving circuit to receive the gate scanning signal as a scanning driving signal, and the sensing circuits of the sub-pixel units in the j-th row are connected to a (j+1)-th output terminal of the gate driving circuit to receive the gate scanning signal as a sensing driving signal.

Abstract: A shift register and a drive method therefor, and a gate drive circuit. The shift register includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit. The detection control sub-circuit is respectively connected to a random detection signal end (OE), a signal input end (INPUT), a first clock signal end (CLKA), a first reset end (RST1), and a pull-up node (PU), and is configured to provide a signal of the first clock signal end (CLKA) for the pull-up node (PU) under the control of the signal input end (INPUT), the random detection signal end (OE), the first clock signal end (CLKA), and the first reset end (RST1).

Abstract: Provided are a display substrate, a manufacturing method thereof and a display apparatus. The display substrate includes multiple sub-pixels, wherein each sub-pixel includes a light-emitting region and a non-light-emitting region, and each sub-pixel is provided with a drive circuit; the drive circuit includes a storage capacitor and multiple transistors; for each sub-pixel, the multiple transistors are in the non-light-emitting region, the storage capacitor is a transparent capacitor, and an orthographic projection of the storage capacitor on a base substrate coincides with the light-emitting region. A first electrode of the storage capacitor is disposed in a same layer as an active layer of the multiple transistors, but in a different layer from source and drain electrodes of the multiple transistors, and a second electrode of the storage capacitor is on a side of the first electrode close to the base substrate.

Abstract: A pixel driving circuit, a display device and an electronic device are provided. The pixel driving circuit includes: a first sub-pixel driving circuit, a second sub-pixel driving circuit, a third sub-pixel driving circuit, and a fourth sub-pixel driving circuit sequentially arranged in a first direction; a detection line; a first power line extending in the second direction; and a second power line extending in the second direction; wherein one of the first power line and the second power line is provided on a side of the second sub-pixel driving circuit away from the third sub-pixel driving circuit, and the other of the first power line and the second power line is provided on a side of the third sub-pixel driving circuit away from the second sub-pixel driving circuit.

Abstract: The present disclosure provides a display panel and an electronic device. The display panel includes: a base substrate; and a pixel arranged on the base substrate, wherein the pixel includes a first sub-pixel including a first sub-pixel drive circuit and a first light emitting element and a second sub-pixel including a second sub-pixel drive circuit and a second light emitting element, the first and second sub-pixel drive circuits are arranged sequentially in a first direction and extend in a second direction, wherein the first light emitting element includes a first anode, the second light emitting element includes a second anode, an orthographic projection of each of the first and the second anodes partially covers an orthographic projections of the first and second sub-pixel drive circuits, and the orthographic projection of the first anode does not overlap the orthographic projection of the second anode.

Abstract: The present application discloses a shift register, a gate driving circuit and a driving method thereof, and a display apparatus. The shift register includes an input sub-circuit, an output sub-circuit, a reset control sub-circuit, a pull-up node reset sub-circuit, and an output signal reset sub-circuit; the input sub-circuit is configured to pre-charge the pull-up node under the control of a signal input to the first signal input terminal; the output sub-circuit is configured to output, through the signal output terminal, a signal input to the first clock signal input terminal under the control of a potential of the pull-up node; the reset control sub-circuit is configured to control, under the control of a reset signal input to the second signal input terminal, whether the pull-up node reset sub-circuit and the output signal reset sub-circuit operate to reset the pull-up node and the signal output terminal, respectively.