Abstract: The present disclosure provides a display substrate, a method for manufacturing the same, a driving method and a display device. The display substrate includes a base substrate, gate lines, data lines and sub-pixels. The sub-pixels include sub-pixel columns corresponding to the data lines in a one-to-one manner. In a sub-pixel driving circuit of the sub-pixel, a driving transistor and a data writing transistor are located at a first side of an aperture area of the sub-pixel; a sensing transistor is located at a second side of the aperture area of the sub-pixel. The first side and the second side are opposite sides of the aperture area along the extension direction of the data lines. Gate electrodes of sensing transistors in a same sub-pixel row, and gate electrodes of data writing transistors in an adjacent next sub-pixel row, are all coupled to a gate line corresponding to the adjacent next sub-pixel row.

Abstract: Disclosed are an apparatus and a method for granulation of a blast furnace slag and recycling of waste heat. The apparatus comprises an aerosol granulation nozzle module, a flow guide, a cyclone separator and a waste heat recovery device; wherein the aerosol granulation nozzle module comprises a slag flow controller, a compressed air flow control valve, a water volume control valve and an aerosol spray gun; the flow guide is configured to fully mix the medium temperature gas and the high-temperature granular slag having a primarily solidified surface in the flow guide; and the cyclone separator is configured to separate the high-temperature granular slag and the medium-to-high-temperature gas. The present invention completes the granulation of blast furnace slag, and organically couples slag sensible heat recovery with sludge drying, thereby recovering the waste heat in the process of slag granulation and improving the efficiency of waste heat recovery and utilization.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a first sub-circuit, a second sub-circuit, and a leakage prevention circuit. The first sub-circuit includes a first input circuit and a first output circuit, the first input circuit is configured to control a level of a first node in response to a first input signal. The second sub-circuit includes a second input circuit and the second output circuit. The leakage prevention circuit is connected to the first node, and is configured to control a level of the leakage prevention node under control of the level of the first node, so that a circuit connected between the first node and the leakage prevention node is turned off, and a circuit connected between the second node and the leakage prevention node is turned off.

Abstract: This application relates to display panels, methods of driving the same, and display devices. The display panel includes: a first pixel circuit and a demultiplexing circuit. The first pixel circuit includes a first reset circuit, a first data writing circuit, and a first drive circuit. A first terminal of the first reset circuit is connected to a first terminal of the first drive circuit. A second terminal of the first reset circuit is connected to a first multiplexing signal line. A control terminal of the first drive circuit is connected to a first terminal of the first data writing circuit. A second terminal of the first data writing circuit is connected to the first multiplexing signal line. The demultiplexing circuit includes a first control circuit and a second control circuit. A first terminal of the first control circuit is connected to the first multiplexing signal line. A second terminal of the first control circuit is used for receiving a reset signal.

Abstract: The present disclosure provides a shift register unit, a signal generation unit circuit, a driving method and a display device. The shift register unit includes a first node control circuit, a second node control circuit and an output circuit, the first node control circuit is used to control a potential of a first node; the second node control circuit controls a potential of a second node; the output circuit is used to control and maintain the potential of the first node and the potential of the second node, and control to connect the output terminal and the second clock signal terminal under the control of the potential of the first node, and control to connect the input terminal and the second voltage terminal under the control of the potential of the second node.

Abstract: A display substrate has a display area and a peripheral area. The display substrate includes a plurality of sub-pixels, a plurality of groups of gate scan signal lines, and a plurality of groups of data lines. Each group of gate scan signal lines includes at least one gate scan signal line, each group of data lines includes n data lines, and the plurality of sub-pixels are arranged in an array; and n is greater than or equal to 2. A group of gate scan signal lines is electrically connected to n rows of sub-pixels. A column of sub-pixels is electrically connected to a group of data lines, and includes a plurality of groups of sub-pixels. Each group of sub-pixels includes n sub-pixels. The n sub-pixels are respectively electrically connected to n data lines in the group of data lines to which this column of sub-pixels is electrically connected.

Abstract: A method for compensating display brightness, a circuit for compensating display brightness, and a display device are provided. The method for compensating display brightness is applicable to a display device. A first group of sub-pixel rows in the display device perform normal display and black frame insertion display in a same frame display period. A second group of sub-pixel rows in the display device perform normal display in a current frame display period and an adjacent next frame display period, and perform black insertion display in the adjacent next frame display period. A first interval period is provided between the current frame display period and the adjacent next frame display period. The method for compensating includes: compensating luminous brightness of the first group of sub-pixel rows and/or compensating luminous brightness of the second group of sub-pixel rows.

Abstract: A multiplexer circuit includes a first selection sub-circuit and a second selection sub-circuit. The first selection sub-circuit configured to transmit an input signal received at a input signal terminal to a first output terminal in response to a first control signal received at a first control terminal, and transmit a voltage of a power supply voltage terminal to the first output terminal in response to a second control signal received at a second control terminal. The second selection sub-circuit configured to transmit the input signal received at the input signal terminal to a second output terminal in response to a third control signal received at a third control terminal, and transmit the voltage of the power supply voltage terminal to the second output terminal in response to a fourth control signal received at a fourth control terminal.

Abstract: The present disclosure provides a shift resister unit, a gate driving circuit, a display device, and a method for controlling a shift register unit. The shift register unit incudes a first input sub-circuit, a first output sub-circuit, a first reset sub-circuit, a second input sub-circuit, and a third input sub-circuit. The first input sub-circuit is configured to change a potential of a first node in a first phase. The first output sub-circuit is configured to output a gate driving signal in the first phase and output a compensation driving signal in a second phase. The first reset sub-circuit is configured to reset the first node. The second input sub-circuit is configured to change a potential of a second node in the first phase and maintain the potential of the second node. The third input sub-circuit is configured to change the potential of the first node in the second phase.

Abstract: A pixel circuit includes a data line, a sensing line, a first pixel sub-circuit and a second pixel sub-circuit. The first pixel sub-circuit includes a first writing unit, a first sensing unit and a first driving unit. The first driving unit is configured to drive a first light-emitting unit to emit light. The second pixel sub-circuit includes a second writing unit, a second sensing unit and a second driving unit. The second driving unit is configured to drive a second light-emitting unit to emit light. The first writing unit and the second sensing unit are both configured to be connected to a gate driving unit. The second writing unit and the first sensing unit are both configured to be connected to another gate driving unit.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a storage capacitor. The storage capacitor includes a second capacitor electrode, a first capacitor electrode and a third capacitor electrode which are sequentially on the base substrate. The first capacitor electrode has a first capacitor electrode side and a second capacitor electrode side opposite to each other in the second direction, and the second capacitor electrode has a third capacitor electrode side and a fourth capacitor electrode side opposite to each other in the second direction; orthographic projections of the first capacitor electrode side and the second capacitor electrode side on the base substrate are between an orthographic projection of the third capacitor electrode side and an orthographic projection of the fourth capacitor electrode side on the base substrate.

Abstract: A shift register unit includes a first input/output unit which includes a first pull-down control circuit and a first auxiliary input circuit, and a second input/output unit which includes a second pull-down control circuit and a second auxiliary input circuit. The first pull-down control circuit controls a level of a first pull-down node. The first auxiliary input circuit is coupled to the first pull-down control circuit and controls the first pull-down control circuit together with a level of a first pull-up node in response to a display control signal and a blanking control signal. The second pull-down control circuit controls a level of a second pull-down node. The second auxiliary input circuit is coupled to the second pull-to down control circuit and controls the second pull-down control circuit together with a level of a second pull-up node in response to the display control signal and the blanking control signal.

Abstract: The present disclosure provides a display substrate and a display device, and belongs to the field of display technology. The display substrate of the present disclosure has a display region, and includes a base and a plurality of data lines and a plurality of fan-out traces on the base; each of the plurality of data lines is connected to a corresponding one of the plurality of fan-out traces at a connection node in the display region; and at least one of the plurality of data lines is connected to a corresponding fan-out trace at a plurality of connection nodes.

Abstract: A display panel (100), comprising: a substrate (1), a plurality of sub-pixels (2) and a gate driving circuit (3). The sub-pixels (2) comprise pixel driving circuits (21). The gate driving circuit (3) comprises multiple stages of cascaded shift registers (31), wherein one stage of shift registers (31) is electrically connected to a plurality of pixel driving circuits (21) in one row of sub-pixels (2). The gate driving circuit (3) further comprises: a plurality of cascaded input signal lines (34) and a plurality of cascaded display reset signal lines (35). Each cascaded input signal line (34) is configured to be connected to a shift signal end (CR<N>) of one stage of shift registers (31) and an input signal end (Iput) of another stage of shift registers (31); and each cascaded display reset signal line (35) is configured to be connected to the shift signal end (CR<N>) of one stage of shift registers (31) and a display reset signal end (STD) of another stage of shift registers.

Abstract: A display panel and a display apparatus are disclosed. The display panel comprises: a plurality of signal lines extending in a first direction; at least one first reference voltage bus which extends in a second direction intersecting the first direction; and a plurality of electrostatic discharge units divided into a plurality of electrostatic discharge unit groups, wherein the plurality of electrostatic discharge unit groups are arranged in the second direction and each of the plurality of electrostatic discharge unit groups comprises at least two electrostatic discharge units arranged in the first direction, wherein at least one of the plurality of signal lines is electrically connected to the first reference voltage bus through at least one of the plurality of electrostatic discharge units.

Abstract: The present disclosure discloses a shift register, a gate driving circuit and a display device. The shift register includes a display pre-charge reset circuit, a sensing cascade circuit, a sensing pre-charge reset circuit, a pull-down control circuit and an output circuit, where the display pre-charge reset circuit, the sensing cascade circuit and the sensing pre-charge reset circuit share the same pull-down control circuit and the same output circuit, the output circuit is coupled to at least one signal output terminal, the output circuit includes output sub-circuits in one-to-one correspondence with the at least one signal output terminal, and each output sub-circuit is configured to write a driving clock signal into the corresponding signal output terminal in a display output stage and a sensing output stage in response to a control of a voltage of a pull-up node in an effective level state.

Abstract: A shift register is provided, which may include a compensation selection circuit, a holding circuit, and N shift register circuits. The hold circuit may hold a blanking input signal. Each of the shift register circuits may include a blanking input circuit and an output circuit. The blanking input circuit may provide a blanking pull-down signal to a first node according to the blanking input signal and a blanking control signal. The output circuit may output a shift signal via a shift signal output terminal and output a first drive signal via a first drive signal output terminal according to a voltage of the first node. The compensation selection circuit may provide, according to a compensation selection control signal and the shift signal from one of the N shift register circuits, the blanking input signal to the holding circuit and the N shift register circuits.

Abstract: A display panel, a display device, and a drive method are provided. The display panel includes a plurality of sub-pixel units arranged in an array and a gate drive circuit, and the array includes N rows. The gate drive circuit includes a plurality of cascaded shift register units and N+1 output terminals arranged in sequence, each of the plurality of cascaded shift register units is configured to output a gate scan signal for driving at least two rows of sub-pixel units in the N rows of the array to work; pixel drive circuits of an (n)-th row of sub-pixel units are connected to an (n)-th output terminal of the gate drive circuit to receive the gate scan signal as a scan drive signal, and sensing circuits of the (n)-th row of sub-pixel units are connected to an (n+1)-th output terminal of the gate drive circuit.

Abstract: A display substrate, including: a base, and a plurality of sub-pixels arranged on the base. At least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element electrically connected to the pixel driving circuit. The pixel driving circuit includes a plurality of transistors and at least one storage capacitor. In a direction perpendicular to the base, the display substrate includes: a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer, which are sequentially arranged on the base. The semiconductor layer includes: an active layer of the plurality of transistors. The first metal layer includes at least a scanning line extending in a first direction, a gate electrode of the plurality of transistors, and a first capacitor electrode plate of the storage capacitor.

Abstract: The present disclosure provides display apparatuses, gate drive circuits, shift register units and driving methods thereof. The shift register unit includes: an outputting module, configured to output a composite output signal under a control of a potential of a pull-up node; a pull-up module, configured to charge the pull-up node under a control of a display control signal terminal and charge the pull-up node under a control of a potential of a black insertion node; a first reset circuit configured to, under a control of the reset signal terminal and the potential of the black insertion node, control a voltage control node to communicate with the pull-up node; a current-limiting circuit, connected between the voltage control node and a first voltage terminal; and a charging module, configured to charge the voltage control node under the control of the potential of the pull-up node.