Abstract: A gate driving unit, a circuit, a display substrate, a display panel, and a display device are provided. The gate driving unit includes an Nth stage of shift register unit and an (N+1)th stage of shift register unit, N is a positive integer. The Nth stage of shift register unit includes an Nth stage of pull-up node control circuit, and the (N+1)th stage of shift register unit includes an (N+1)th stage of pull-up node control circuit. The Nth stage of pull-up node control circuit is electrically connected to an Nth stage of pull-up node and a control line, respectively, is configured to control a potential of the Nth stage of pull-up node under the control of a control signal inputted by the control line. The (N+1)th stage of pull-up node control circuit is electrically connected to an (N+1)th stage of pull-up node and the control line, respectively, and is configured to control a potential of the (N+1)th stage of pull-up node under the control of the control signal inputted by the control line.

Abstract: The present disclosure provides a display panel and an electronic device. The display panel includes: a base substrate; and a pixel arranged on the base substrate, wherein the pixel includes a first sub-pixel including a first sub-pixel drive circuit and a first light emitting element and a second sub-pixel including a second sub-pixel drive circuit and a second light emitting element, the first and second sub-pixel drive circuits are arranged sequentially in a first direction and extend in a second direction, wherein the first light emitting element includes a first anode, the second light emitting element includes a second anode, an orthographic projection of each of the first and the second anodes partially covers an orthographic projections of the first and second sub-pixel drive circuits, and the orthographic projection of the first anode does not overlap the orthographic projection of the second anode.

Abstract: A display substrate including a plurality of light emitting elements respectively in a plurality of subpixels configured to emit light for image display is provided. A respective one of the plurality of subpixels includes a base substrate; a first auxiliary cathode; a passivation layer; a first insulating layer; a second auxiliary cathode; a second insulating layer; and a pixel definition layer. The display substrate has a cathode aperture extending through the pixel definition layer and an auxiliary cathode aperture extending through the first insulating layer and the passivation layer. A cathode of a respective one of the plurality of light emitting elements extends into the cathode aperture to electrically connect with the second auxiliary cathode. The second auxiliary cathode extends into the auxiliary cathode aperture to electrically connect with the first auxiliary cathode.

Abstract: Disclosed is a shift register unit set, a gate driving circuit and a display apparatus, the shift register set including: cascaded n shift register units, and an ith stage of shift register unit in the shift register unit set includes: a first input sub-circuit and a second input sub-circuit, wherein the first input sub-circuit includes: a charging sub-circuit, a storing sub-circuit, an isolating sub-circuit, an output sub-circuit, a first electric leakage prevention sub-circuit configured to input an operation potential to the isolating sub-circuit under the control of the blanking pull-up control node, and a second electric leakage prevention sub-circuit configured to input the operation potential to a second electrode of the isolating transistor under the control of the first pull-up node, wherein there is an overlap among n composite output signals output by the n shift register units, n and i are positive integers, and 1?i?n.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels which are arranged in a sub-pixel array in a first direction and a second direction. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. An active layer of the third transistor includes a body region and a first via hole region successively arranged in the first direction and electrically connected with each other; a first electrode of the third transistor is electrically connected to the first via hole region through a first via hole which is shifted in the second direction with respect to the body region, allowing the active layer incudes a first active layer side connecting the body region and the first via hole region; an extension direction of the first active layer side intersects with both the first direction and the second direction.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: The present disclosure relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display panel.

Abstract: A shift-register unit circuit (100) includes a first input sub-circuit (120) configured to receive a display-input signal from a display-input terminal (STU2, VDD, VGH) and input a display output-control signal to a first node (Q) based on the display-input signal during a display period of one cycle of displaying one frame of image. The shift-register unit circuit (100) also includes a second input sub-circuit (110) configured to receive a blank-input signal for charging a blank-control node (H), and configured to input a blank-output-control signal to the first node (Q) based on the blank-input signal during a blank period of the one cycle. The shift-register unit circuit (100) further includes an output sub-circuit (130) configured to output a hybrid signal controlled by the first node (Q). The second input sub-circuit (110) is also configured, before an end of the blank period, to receive a first blank-reset signal to reset the blank-control node (H).

Abstract: An array substrate and a detection method thereof, and a display panel are disclosed. The array substrate includes a plurality of subpixels and a plurality of signal line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each signal line structure of the plurality of signal line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, and the signal line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking unit, a first transmission circuit and a first input-output unit. The blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node. The first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node; and the first input-output unit includes a first leakage preventing structure, the first leakage preventing structure is electrically connected to the first pull-up node and a first leakage preventing node respectively, and the leakage preventing structure is configured to control a level of the first leakage preventing node under the control of the level of the first pull-up node to prevent the first pull-up node from leaking.

Abstract: Provided are a pixel circuit, a driving method thereof and a display panel. The pixel circuit includes: multiple sub-pixel circuits in an array; each sub-pixel circuit includes a first node control sub-circuit, a second node control sub-circuit, a driving sub-circuit, a storage sub-circuit, a reading sub-circuit and a light emitting device; at least reading sub-circuits of the sub-pixel circuits of some rows are controlled by a same sensing control line; the first node control sub-circuit charges the storage sub-circuit in response to a first scan signal; the second node control sub-circuit writes a reference voltage signal into a second node in response to a second scan signal; the reading sub-circuit reads a potential of the second node in response to a sensing control signal written by a sensing control line; the driving sub-circuit drives the light emitting device to emit light.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A shift register driving method includes: in a black insertion driving period, the black insertion input circuit, in response to a black insertion control signal, causing the output circuit to first output a first sense driving signal and a second sense driving signal, so that the control electrode of the switching transistor receives the first sense driving signal to turn on the switching transistor, the first electrode of the switching transistor receives a sensing data signal, and the control electrode of the sensing transistor receives the second sense driving signal to turn on the sensing transistor, and a second electrode of the sensing transistor outputs a pixel compensation signal, at the same time the sub-pixel stops emitting light; the output circuit outputs a black insertion driving signal, and the pixel circuit receives the black insertion driving signal to turn off the driving transistor, and the sub-pixel keeps not emitting light.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking unit, a first transmission circuit, and a first input-output unit. The blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node. The first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node. The first input-output unit includes an output circuit, a first pull-down control circuit, and a first pull-down auxiliary control circuit.

Abstract: The present disclosure provides display apparatuses, gate drive circuits, shift register units and driving methods thereof. The shift register unit includes: an outputting module, configured to output a composite output signal under a control of a potential of a pull-up node; a pull-up module, configured to charge the pull-up node under a control of a display control signal terminal and charge the pull-up node under a control of a potential of a black insertion node; a first reset circuit configured to, under a control of the reset signal terminal and the potential of the black insertion node, control a voltage control node to communicate with the pull-up node; a current-limiting circuit, connected between the voltage control node and a first voltage terminal; and a charging module, configured to charge the voltage control node under the control of the potential of the pull-up node.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a banking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node, wherein the composite output signal includes a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A shift register and a drive method therefor, and a gate drive circuit. The shift register includes: an input sub-circuit, a detection control sub-circuit, an output sub-circuit, a first reset sub-circuit, and a pull-down sub-circuit. The detection control sub-circuit is respectively connected to a random detection signal end (OE), a signal input end (INPUT), a first clock signal end (CLKA), a first reset end (RST1), and a pull-up node (PU), and is configured to provide a signal of the first clock signal end (CLKA) for the pull-up node (PU) under the control of the signal input end (INPUT), the random detection signal end (OE), the first clock signal end (CLKA), and the first reset end (RST1).

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array in a first direction and a second direction, the first direction intersecting with the second direction. The display substrate further includes data lines extended in the first direction, and the data lines are connected in one-to-one correspondence with the sub-pixels in columns in each row of sub-pixels, so as to provide data signals respectively; the display substrate further includes auxiliary electrode lines extended in the first direction which are configured to be electrically connected with a second electrode of the light emitting element to provide a second power voltage; each of the auxiliary electrode lines is spaced from any one of the plurality of data lines by at least one column of sub-pixels.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output an output blanking output control signal; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal; a selection sub-circuit, having a first terminal connected to the second input sub-circuit, a second terminal connected to the first input sub-circuit, and a third terminal connected to a first node, configured to control a potential of the first node according to the display output control signal and the blanking output control signal; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node.

Abstract: Brightness compensation method and apparatus for pixel point are provided. The compensation method includes measurement processes of N times, N?2.