Abstract: The present disclosure provides a shift register unit, a gate driving circuit and compensation method and driving method thereof, and a display device. The shift register unit includes: a shift register circuit having a detection node, the shift register circuit is configured to receive an input signal and a clock signal, and generate an output signal based on the clock signal under control of the input signal; and a detection circuit coupled to the detection node of the shift register circuit, the detection circuit is configured to generate a detection signal based on a potential of the detection node.

Abstract: The present disclosure discloses a shift register, a gate driving circuit and a display device. The shift register includes a display pre-charge reset circuit, a sensing cascade circuit, a sensing pre-charge reset circuit, a pull-down control circuit and an output circuit, where the display pre-charge reset circuit, the sensing cascade circuit and the sensing pre-charge reset circuit share the same pull-down control circuit and the same output circuit, the output circuit is coupled to at least one signal output terminal, the output circuit includes output sub-circuits in one-to-one correspondence with the at least one signal output terminal, and each output sub-circuit is configured to write a driving clock signal into the corresponding signal output terminal in a display output stage and a sensing output stage in response to a control of a voltage of a pull-up node in an effective level state.

Abstract: Disclosed is a shift register, a gate driving circuit, a display apparatus and a driving method, the shift register including a first input sub-circuit configured to receive a first input signal from a first input terminal and output a banking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of a first node, wherein the composite output signal includes a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: A pixel circuit and a driving method thereof, and a display device, the pixel circuit being configured to drive a light-emitting element and including: a node control sub-circuit, which is configured to provide a first node with a signal of a data signal end and provide a second node with a signal of a control signal end under the control of a first scanning end; a driving sub-circuit, which is configured to provide the second node with a driving current under the control of the first node and the second node; a storage sub-circuit, which is configured to store electric charge between the first node and the second node; a reading sub-circuit, and the light-emitting element, which is electrically connected to the second node and a second power supply end, respectively.

Abstract: A display substrate and a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. The sub-pixels are arranged in a sub-pixel array. At least one sub-pixel includes a first transistor, a second transistor, a third transistor and a storage capacitor. The first electrode of the third transistor is electrically connected to an active layer of the third transistor through a first via hole, and the first electrode of the third transistor is configured to be electrically connected to the light emitting element through a second via hole; the first via hole and the second via hole are at least partially overlapped with each other in a direction perpendicular to the base substrate.

Abstract: A shift register is provided, which includes a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, and a shift register circuit. The blanking input circuit may provide a blanking input signal to a first control node according to a second clock signal. The blanking control circuit may provide a first clock signal to a second control node and maintain a voltage difference between the first control node and the second control node, according to a voltage of the first control node. The blanking pull-down circuit may provide a voltage of the second control node to a pull-down node according to the first clock signal. The shift register circuit may provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal according to a voltage of the pull-down node.

Abstract: A shift register unit includes a first node connection branch, an ON/OFF control circuit and a third node control circuit. A first end of the first node connection branch is electrically connected to first node, and a second end of the first node connection branch is electrically connected to a third node. The first node connection branch is configured to control the first node to be electrically connected to the third node under the control of a potential at the first node. The ON/OFF control circuit is configured to control the third node to be electrically connected to a first voltage end under the control of the potential at the first node. The third node control circuit is configured to reset a potential at the third node under the control of a resetting signal from a resetting end and a potential at a second node.

Abstract: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.

Abstract: Disclosed are a display substrate and a display device. A display region and a peripheral region are included. The peripheral region includes a plurality of shift registers and a plurality of clock signal lines. The plurality of clock signal lines are arranged side by side in a first direction and include a first clock signal line to a Zth clock signal line, Z?1. The shift registers are connected with gate lines in the display region and the first clock signal line to the Zth clock signal line respectively. There is at least a group of ith clock signal lines satisfying that the ith clock signal lines include X ith clock signal lines which are arranged one by one according to a sequence of connection with shift registers and further include N ith clock signal lines.

Abstract: A display substrate including a plurality of light emitting elements respectively in a plurality of subpixels configured to emit light for image display is provided. A respective one of the plurality of subpixels includes a base substrate; a first auxiliary cathode; a passivation layer; a first insulating layer; a second auxiliary cathode; a second insulating layer; and a pixel definition layer. The display substrate has a cathode aperture extending through the pixel definition layer and an auxiliary cathode aperture extending through the first insulating layer and the passivation layer. A cathode of a respective one of the plurality of light emitting elements extends into the cathode aperture to electrically connect with the second auxiliary cathode. The second auxiliary cathode extends into the auxiliary cathode aperture to electrically connect with the first auxiliary cathode.

Abstract: A display panel includes a plurality of pixel driving circuits and a plurality of sense lines. The pixel driving circuits are capable of being divided into a plurality of rows of pixel driving circuits each arranged in a first direction and divided into a plurality of columns of pixel driving circuit each arranged in a second direction intersected with the first direction. Each pixel driving circuit includes a detection transistor. The sense lines are arranged at intervals and extending along the second direction, and are configured to provide reference voltage signals to the plurality of pixel driving circuits. Each detection transistor is electrically connected to one of the plurality of sense lines, and in pixel driving circuits in a same column, detection transistors in any two adjacent rows are electrically connected to different sense lines.

Abstract: There is provided a driving method for a pixel circuit including a driving transistor, a data writing circuit, a sensing circuit, and a storage capacitor. The driving method includes: during a sensing write stage, writing a test voltage equal to a sum of a first reference voltage and a threshold voltage of the driving transistor, by the data writing circuit, to the control electrode of the driving transistor, and writing a second reference voltage, by the sensing circuit, to a second electrode of the driving transistor; during a sensing sampling stage, continuing to write the test voltage to the control electrode of the driving transistor by the data writing circuit, and stopping writing a voltage to the second electrode of the driving transistor by the sensing circuit. The driving method further includes a sensing reset stage and a sensing charging stage.

Abstract: A shift register unit includes a pull-down sustaining sub-circuit and a pull-down sub-circuit. The pull-down sustaining sub-circuit includes: a first transistor having a control electrode configured to input a pull-down sustaining signal, a first electrode connected to a first power signal terminal, and a second electrode connected to a pull-down node; a first capacitor; and a second transistor having a control electrode connected to an input signal terminal. The pull-down sub-circuit includes: a third transistor having a control electrode connected to the first terminal of the first capacitor, a first electrode connected to a pull-up node, and a second electrode connected to the second power signal terminal; a fourth transistor having a control electrode connected to the first terminal of the first capacitor, a first electrode connected to an output sub-circuit, and a second electrode connected to the second power signal terminal.

Abstract: The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes a first input sub-circuit to an Nth input sub-circuit and a first output sub-circuit to an Nth output sub-circuit. N is an integer greater than or equal to 2. For n=1, 2, . . . , N, an nth input sub-circuit is electrically coupled to an nth input signal terminal, a first level signal terminal and a pull-up node, and an nth output sub-circuit is electrically coupled to an nth clock signal terminal, the pull-up node and an nth output signal terminal.

Abstract: A pixel structure includes: gate lines and data lines disposed crosswise and a plurality of pixel repetition modules distributed in an array. A pixel repetition module includes: a plurality of pixel units arranged in order, wherein each pixel unit includes three sub-pixels arranged in a triangular structure, and the three sub-pixels in each pixel unit and the three sub-pixels in an adjacent pixel unit are arranged inversely with respect to each other; each pixel unit corresponds to two groups of gate lines, wherein each group of gate lines includes two gate lines parallel to each other, a first group of gate lines are located on a first outer side and a second outer side of the pixel units respectively, and a second group of gate lines are both located between the sub-pixels located in a first row and the sub-pixels located in a second row in the pixel units.

Abstract: A shift register unit, a gate drive circuit, a display panel, a display device and a driving method. The shift register unit includes a first input circuit, a second input circuit, a first output circuit, a second output circuit, a first reset circuit and a second reset circuit. The first input circuit is configured to control a level of a first node in response to a first input signal. The second input circuit is configured to control the level of the first node in response to a second input signal. The first output circuit is configured to output a first clock signal to a first output terminal under a control of the level of the first node. The second output circuit is configured to output a second clock signal to a second output terminal under the control of the level of the first node.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking input circuit, a blanking control circuit, a blanking coupling circuit, a display input circuit and an output circuit. The blanking input circuit is configured to charge a control node in response to a compensation selection control signal, and to maintain a level of the control node. The blanking control circuit is configured to charge a first node, by using a first clock signal, under control of the level of the control node and the first clock signal. The blanking coupling circuit is electrically connected to the control node, and is configured to control, by coupling, the level of the control node in response to the first clock signal.

Abstract: A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node.

Abstract: A shift register unit, a grid drive circuit, a display device and a driving method are disclosed. The shift register unit includes a display sub-shift-register and a detection sub-shift-register. The display sub-shift-register includes a display output terminal, and the display sub-shift-register is configured to output a display output signal of the shift register unit from the display output terminal at a display stage; the detection sub-shift-register is connected to a display output terminal of the display sub-shift-register to receive a display output signal, and includes a first random pulse signal terminal to receive a first random pulse signal. The detection sub-shift-register is configured to output a detection output signal of the shift register unit when the display output signal is at a turn-on level and the first random pulse signal is at a turn-on level.

Abstract: A shift register unit, a gate driving circuit, a display device, and a method for controlling a shift register unit are provided. The shift register unit includes a first input sub-circuit, a second input sub-circuit, a first isolation sub-circuit, and a first output sub-circuit. The first input sub-circuit is configured to control a potential of a first node. The second input sub-circuit is configured to control a potential of a second node. The first isolation sub-circuit is configured to control conduction and interruption of electrical coupling between the first node and the second node. The first output sub-circuit is configured to output a gate driving signal in a display phase and output a compensation driving signal in a field blanking phase.