Abstract: The present disclosure relates to a display method of a display panel. The display method may include obtaining original luminance of three single color subpixels in each of the pixel units based on an image to be displayed; obtaining luminance compensation values of the three single color subpixels that need to be color compensated at a time of obtaining the luminance of the mixed color subpixel as the first substitute luminance; calculating luminance of the mixed color produced by the three single color subpixels in the pixel unit respectively based on each of the luminance of the three single color subpixels after color compensation; and setting input luminance of the single color subpixel having the smallest luminance of the mixed color as 0, and obtaining actual luminance of the other single color subpixels and the mixed color subpixel.

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate and sub-pixels on the base substrate. At least one sub-pixel includes a first transistor, a second transistor, a third transistor, and a storage capacitor. The display substrate further includes an extension portion protruding from the gate electrode of the first transistor, and the extension portion is extended from the gate electrode of the first transistor in the second direction; the extension portion is at least partially overlapped with the first electrode of the second transistor in a direction perpendicular to the base substrate and is electrically connected with the first electrode of the second transistor; in the first direction, the extension portion has a second side closest to the second capacitor electrode, and the second side is recessed in a direction away from the second capacitor electrode.

Abstract: A shift register unit and a control method thereof, a gate driving circuit and a control method thereof, and a display apparatus are provided. The shift register unit includes: a first shift register coupled to an input signal terminal, a first clock signal terminal and a second clock signal terminal. The first shift register is configured to generate a first output signal based on the signal at the first clock signal terminal and generate a second output signal based on the signal at the second clock signal terminal; and a second shift register coupled to the input signal terminal and a third clock signal terminal, the second shift register is configured to generate a third output signal based on the signal at the third clock signal terminal. The first shift register includes a first control circuit, a first output circuit and a second output circuit.

Abstract: Provided in the present disclosure are a display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of display units, each display unit comprising a display area and a transparent area, and the display area comprising a plurality of sub-pixels; each sub-pixel comprises a second metal layer and a third metal layer, the second metal layer comprising a first scanning line and a second scanning line defining a display row, the third metal layer comprising a first power source line, a second power source line, a compensation line, and a data line defining the plurality of sub-pixels; the first power source line, the second power source line, the compensation line, and the data line all comprise a vertical linear section and a horizontal polyline section.

Abstract: A shift register and a method of driving the same, a gate driving circuit, and a display panel are disclosed. The shift register includes a display control circuit coupled to a pull-up node, a first power supply and a first control terminal respectively; a cascade output circuit coupled to a second clock terminal, the pull-up node and a cascade output terminal; a sensing control circuit coupled to the pull-up node, the cascade output terminal, a second control terminal and a third control terminal respectively; and a signal output circuit coupled to the pull-up node, a first clock terminal and a signal output terminal.

Abstract: An array substrate includes an array of a plurality of subpixels including a plurality of columns of subpixels respectively spaced apart by a plurality of inter-subpixel regions; a plurality of pixel driving circuits respectively driving light emission of the plurality of subpixels; and a plurality of detection and compensation lead lines respectively configured to respectively detect signals in the plurality of subpixels and respectively compensate signals in the plurality of subpixels. A respective one of a plurality of detection and compensation lead lines is disposed in a first inter-subpixel region between two directly adjacent columns of subpixels. The respective one of the plurality of detection and compensation lead lines is spaced apart by at least one columns of subpixels from a signal line configured to transmit an alternating current and arranged along a direction parallel to the respective one of the plurality of detection and compensation lead lines.

Abstract: The present disclose is related to an array substrate. The array substrate may include a base substrate; a driving transistor on the base substrate; an insulating layer on the driving transistor, the insulating layer comprising a via hole above a first electrode of the driving transistor; a conductive portion on the insulating layer; and a light emitting device on the conductive portion and electrically connected to the conductive portion. The conductive portion may be electrically connected to the first electrode of the driving transistor through the via hole. The light emitting device may be above the via hole, and an orthographic projection of the light emitting device on the base substrate may cover an orthographic projection of the via hole on the base substrate.

Abstract: A display panel and a display device are disclosed. The display panel includes a plurality of sub-pixel units arranged in an array which includes N rows and 4M columns, sub-pixel units in each row is divided into a plurality of sub-pixel unit groups, and each sub-pixel unit group includes a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit and a fourth sub-pixel unit which are sequentially in four adjacent columns along a first direction.

Abstract: Provided are a display substrate and a preparation method therefor, and a display apparatus, which can not only avoid jumpers generated when a light-emitting device in a sub-pixel is electrically connected to a storage capacitor, in order to avoid the risk of crosstalk, but can also increase the pixel aperture ratio of the display substrate and increase the capacitance of the storage capacitor in a pixel driving circuit.

Abstract: A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node; the first input circuit includes a first transistor and a first capacitor, and a second electrode of the first capacitor is connected to the first electrode of the first transistor.

Abstract: A display substrate includes: a base; a cathode power line disposed on the base and located in the peripheral region; a first insulating layer located on a side of a layer in which the cathode power line is located away from the base and having first via hole(s); a cathode layer located on the first insulating layer and electrically connected to the cathode power line through the first via hole(s); and spacer(s) located on a side of the cathode layer proximate to the base, a spacer covering at least a side wall of a first via hole, a thickness of a portion of the spacer covering the side wall decreasing along the side wall and in a direction pointing from an end of the side wall proximate to the base toward an end of the side wall of the first via hole away from the base.

Abstract: The present disclosure provides a shift register unit, including a detection signal input sub-circuit, a display signal input sub-circuit, an output circuit, a pull-down control circuit and a signal output terminal, the output circuit includes a pull-up sub-circuit and a pull-down sub-circuit, the pull-down control circuit includes a selection sub-circuit and a plurality of pull-down control sub-circuits. The present disclosure further provides a gate driving circuit, a display panel and a driving method for driving the display panel. The shift register unit has a simple structure and a long service life.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: Embodiments of the present disclosure provide a shift register circuitry, a gate driving circuit, a display device, and a driving method. The shift register circuitry includes a blanking input circuit, a display input circuit, an output circuit, and a first control circuit. The blanking input circuit provides a blanking input signal to the pull-up control node and supplies a blanking pull-up signal to the pull-up node. The display input circuit provides a display pull-up signal to the pull-up node in response to the display input signal. The output circuit outputs the output signal to the shift signal output terminal and the pixel signal output terminal under the control of the voltage of the pull-up node. The first control circuit couples the shift signal output terminal to the pixel signal output terminal in response to the display input signal.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are disclosed. The shift register unit includes a blanking unit, a first transmission circuit, a second transmission circuit, a first input-output unit, and a second input-output unit. The blanking unit is configured to charge a pull-up control node in response to a compensation selection control signal and input a blanking pull-up signal to a blanking pull-up node. The first transmission circuit is electrically connected to the blanking pull-up node and the first pull-up node, and the second transmission circuit is electrically connected to the blanking pull-up node and the second pull-up node.

Abstract: A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit and the second input circuit have a same circuit structure.

Abstract: A shift register unit, a gate driving circuit, a display device, and a driving method are provided. The shift register unit includes a first input circuit, an output control circuit, and an output circuit. The first input circuit is configured to output a first input signal to a first node in response to a first control signal; the output control circuit is configured to output an output control signal to a second node under control of a level of the first node; and the output circuit includes an output terminal, and the output circuit is configured to output an output signal to the output terminal under control of a level of the second node.

Abstract: A shift register unit, a gate drive circuit, a display device and a driving method are provided. The shift register unit includes a sub-shift register, a second sub-shift register and an output control circuit. The first sub-shift register includes a first output terminal and a first control node, and is configured to output a first clock signal under control of a level of the first control node. The second sub-shift register include a second output terminal and a second control node, and the second output terminal outputs a display output signal in a display phase and a random output signal in a blank phase under control of a level of the second control node. The output control circuit is connected to the first sub-shift register and the second control node, and is configured to control the level of the second control node under control of an output control signal.

Abstract: Provided are a shift register unit circuit and drive method, and a gate driver and a display device. The shift register unit circuit includes a first sub-unit circuit, a second sub-unit circuit, a third sub-unit circuit, and a fourth sub-unit circuit. Responsive to providing a corresponding input pulse and clock signal, the shift register unit circuit is configured output first, second, third, and fourth output signals. The shift register unit circuit is configured such that a fifth node is in conduction with a second node at least while the reset pulse is active.

Abstract: A shift register includes a first reset circuit having a first transistor and a second transistor, and a selection control circuit connected to a pull-down node, and control electrodes of the first and second transistors. First electrodes of the first and second transistors are connected to a first voltage terminal, and second electrodes of the first and second transistors are connected to a signal output terminal. The selection control circuit is configured to: control a line between the pull-down node and the control electrode of the first transistor, and a line between the pull-down node and the control electrode of the second transistor to be alternately closed. The first reset circuit is configured to output a voltage of the first voltage terminal to the signal output terminal under control of a potential at the pull-down node transmitted by the selection control circuit.